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axi_ad9963: Separated adc/dac clock and reset

main
Adrian Costina 2017-03-29 11:01:44 +03:00 committed by Lars-Peter Clausen
parent 6a49aefb6c
commit 094872619d
2 changed files with 16 additions and 17 deletions
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15
library/axi_ad9963/axi_ad9963.v
View File

@ -71,9 +71,10 @@ module axi_ad9963 #(
// master interface
output l_clk,
output adc_clk,
output dac_clk,
output rst,
output adc_rst,
output dac_rst,
// dma interface
@ -158,8 +159,6 @@ module axi_ad9963 #(
wire [31:0] up_rdata_tx_s;
wire up_rack_tx_s;
wire dac_rst;
// signal name changes
assign up_clk = s_axi_aclk;
@ -186,8 +185,8 @@ module axi_ad9963 #(
.tx_clk (tx_clk),
.tx_iq (tx_iq),
.tx_data (tx_data),
.rst (rst),
.l_clk (l_clk),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.adc_valid (adc_valid_s),
@ -209,8 +208,8 @@ module axi_ad9963 #(
.ID (ID),
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
i_rx (
.adc_rst (rst),
.adc_clk (l_clk),
.adc_rst (adc_rst),
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_status (adc_status_s),

18
library/axi_ad9963/axi_ad9963_if.v
View File

@ -52,10 +52,10 @@ module axi_ad9963_if #(
// clock (common to both receive and transmit)
input rst,
output l_clk,
output dac_clk,
input adc_rst,
input dac_rst,
output adc_clk,
output dac_clk,
// receive data path interface
@ -96,7 +96,7 @@ module axi_ad9963_if #(
genvar l_inst;
always @(posedge l_clk) begin
always @(posedge adc_clk) begin
if( rx_iq_p_s == 1'b1) begin
adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I
adc_valid <= 1'b1; // data[23:12] Q
@ -114,8 +114,8 @@ module axi_ad9963_if #(
end
end
always @(posedge l_clk) begin
if (rst == 1'b1) begin
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
end else begin
adc_status <= 1'b1;
@ -126,7 +126,7 @@ module axi_ad9963_if #(
BUFG i_clk_gbuf (
.I (trx_clk),
.O (l_clk));
.O (adc_clk));
// receive data interface, ibuf -> idelay -> iddr
@ -138,7 +138,7 @@ module axi_ad9963_if #(
.IODELAY_CTRL (0),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_data (
.rx_clk (l_clk),
.rx_clk (adc_clk),
.rx_data_in_p (trx_data[l_inst]),
.rx_data_in_n (1'b0),
.rx_data_p (rx_data_p_s[l_inst]),
@ -161,7 +161,7 @@ module axi_ad9963_if #(
.IODELAY_CTRL (1),
.IODELAY_GROUP (IO_DELAY_GROUP))
i_rx_iq (
.rx_clk (l_clk),
.rx_clk (adc_clk),
.rx_data_in_p (trx_iq),
.rx_data_in_n (1'b0),
.rx_data_p (rx_iq_p_s),