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axi_ad9783: Initial commit

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Iulia Moldovan 2022-01-07 13:25:42 +02:00 committed by imoldovan
parent fcd3bfd349
commit 08f029c757
6 changed files with 927 additions and 0 deletions
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library/axi_ad9783/Makefile Executable file
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####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ad9783
GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_2.v
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9783.v
GENERIC_DEPS += axi_ad9783_channel.v
GENERIC_DEPS += axi_ad9783_core.v
GENERIC_DEPS += axi_ad9783_if.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/ad_serdes_out.v
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9783_ip.tcl
include ../scripts/library.mk

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library/axi_ad9783/axi_ad9783.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9783 #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter SERDES_OR_DDR_N = 1,
parameter MMCM_OR_BUFIO_N = 1,
parameter DAC_DDS_TYPE = 2,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DAC_DATAPATH_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
// dac interface
// from dco1_p
input dac_clk_in_p,
// from dco1_n
input dac_clk_in_n,
// to dci_p
output dac_clk_out_p,
// to dci_n
output dac_clk_out_n,
output [ 15:0] dac_data_out_p,
output [ 15:0] dac_data_out_n,
// dma interface
output dac_div_clk,
output dac_rst,
output dac_valid,
output dac_enable_0,
output dac_enable_1,
input [ 63:0] dac_ddata_0,
input [ 63:0] dac_ddata_1,
input dac_dunf,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal clocks and resets
wire dac_rst_s;
wire up_clk;
wire up_rstn;
// internal signals
wire [ 15:0] dac_data_a0_s;
wire [ 15:0] dac_data_a1_s;
wire [ 15:0] dac_data_a2_s;
wire [ 15:0] dac_data_a3_s;
wire [ 15:0] dac_data_b0_s;
wire [ 15:0] dac_data_b1_s;
wire [ 15:0] dac_data_b2_s;
wire [ 15:0] dac_data_b3_s;
wire dac_status_s;
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign dac_rst = dac_rst_s;
// device interface
axi_ad9783_if #(
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_rst (dac_rst_s),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_data_a0 (dac_data_a0_s),
.dac_data_a1 (dac_data_a1_s),
.dac_data_a2 (dac_data_a2_s),
.dac_data_a3 (dac_data_a3_s),
.dac_data_b0 (dac_data_b0_s),
.dac_data_b1 (dac_data_b1_s),
.dac_data_b2 (dac_data_b2_s),
.dac_data_b3 (dac_data_b3_s));
// core
axi_ad9783_core #(
.ID(ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst_s),
.dac_data_a0 (dac_data_a0_s),
.dac_data_a1 (dac_data_a1_s),
.dac_data_a2 (dac_data_a2_s),
.dac_data_a3 (dac_data_a3_s),
.dac_data_b0 (dac_data_b0_s),
.dac_data_b1 (dac_data_b1_s),
.dac_data_b2 (dac_data_b2_s),
.dac_data_b3 (dac_data_b3_s),
.dac_status (dac_status_s),
.dac_valid (dac_valid),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dunf (dac_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9783/axi_ad9783_channel.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9783_channel #(
parameter CHANNEL_ID = 32'h0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
// dac interface
input dac_div_clk,
input dac_rst,
output reg dac_enable,
output reg [15:0] dac_data0,
output reg [15:0] dac_data1,
output reg [15:0] dac_data2,
output reg [15:0] dac_data3,
input [63:0] dma_data,
// processor interface
input dac_data_sync,
input dac_dds_format,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// internal signals
wire [63:0] dac_dds_data_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
reg [23:0] dac_prbs_data = 'd0;
reg [15:0] dac_prbs_counter = 'd0;
// pn23 function
function [23:0] pn23;
input [23:0] din;
reg [23:0] dout;
begin
dout = {din[22:0], din[22] ^ din[17]};
pn23 = dout;
end
endfunction
// dac data select
always @(posedge dac_div_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h2: begin
dac_data0 <= dma_data[15: 0];
dac_data1 <= dma_data[31:16];
dac_data2 <= dma_data[47:32];
dac_data3 <= dma_data[63:48];
end
4'h3: begin
dac_data0 <= 16'h0;
dac_data1 <= 16'h0;
dac_data2 <= 16'h0;
dac_data3 <= 16'h0;
end
4'h9: begin
dac_data0 <= dac_prbs_data[15:0];
dac_data1 <= dac_prbs_data[23:8];
dac_data2 <= dac_prbs_data[15:0];
dac_data3 <= dac_prbs_data[23:8];
end
default: begin
dac_data0 <= dac_dds_data_s[15: 0];
dac_data1 <= dac_dds_data_s[31:16];
dac_data2 <= dac_dds_data_s[47:32];
dac_data3 <= dac_dds_data_s[63:48];
end
endcase
end
always @(posedge dac_div_clk) begin
if(dac_data_sel_s != 9) begin
dac_prbs_data <= 24'hffffff;
dac_prbs_counter <= 16'h0;
end else begin
if (dac_prbs_counter == 4096) begin
dac_prbs_data <= 24'h0;
end else begin
dac_prbs_data <= pn23(dac_prbs_data);
dac_prbs_counter <= dac_prbs_counter + 1;
end
end
end
// dds
ad_dds #(
.DISABLE (DATAPATH_DISABLE),
.DDS_DW (16),
.PHASE_DW (16),
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.CLK_RATIO (4))
i_dds (
.clk (dac_div_clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
.dac_valid (1'b1),
.tone_1_scale (dac_dds_scale_1_s),
.tone_2_scale (dac_dds_scale_2_s),
.tone_1_init_offset (dac_dds_init_1_s),
.tone_2_init_offset (dac_dds_init_2_s),
.tone_1_freq_word (dac_dds_incr_1_s),
.tone_2_freq_word (dac_dds_incr_2_s),
.dac_dds_data (dac_dds_data_s));
// single channel processor
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iq_mode (),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9783/axi_ad9783_core.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9783_core #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_CORDIC_DW = 16,
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0) (
// dac interface
input dac_div_clk,
output dac_rst,
output [ 15:0] dac_data_a0,
output [ 15:0] dac_data_a1,
output [ 15:0] dac_data_a2,
output [ 15:0] dac_data_a3,
output [ 15:0] dac_data_b0,
output [ 15:0] dac_data_b1,
output [ 15:0] dac_data_b2,
output [ 15:0] dac_data_b3,
input dac_status,
// dma interface
output dac_valid,
output dac_enable_0,
output dac_enable_1,
input [ 63:0] dac_ddata_0,
input [ 63:0] dac_ddata_1,
input dac_dunf,
// processor interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 13:0] up_raddr,
output reg [ 31:0] up_rdata,
output reg up_rack);
// internal registers
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [ 31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [ 31:0] up_rdata_1_s;
wire up_rack_1_s;
wire up_wack_1_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
wire dac_enable_0_reg;
wire dac_enable_1_reg;
// defaults
assign dac_valid = 1'b1;
assign dac_enable_0 = dac_enable_0_reg;
assign dac_enable_1 = dac_enable_1_reg;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
end
end
// dac channel
axi_ad9783_channel #(
.CHANNEL_ID(0),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_0_reg),
.dac_data0 (dac_data_a0),
.dac_data1 (dac_data_a1),
.dac_data2 (dac_data_a2),
.dac_data3 (dac_data_a3),
.dma_data (dac_ddata_0),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
axi_ad9783_channel #(
.CHANNEL_ID(1),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.DATAPATH_DISABLE(DATAPATH_DISABLE))
i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_1_reg),
.dac_data0 (dac_data_b0),
.dac_data1 (dac_data_b1),
.dac_data2 (dac_data_b2),
.dac_data3 (dac_data_b3),
.dma_data (dac_ddata_1),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_1_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_1_s),
.up_rack (up_rack_1_s));
// dac common processor interface
up_dac_common #(
.ID (ID),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd16),
.up_dac_ce (),
.up_pps_rcounter (31'd0),
.up_pps_status (1'd0),
.up_pps_irq_mask (),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd1),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd1),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9783/axi_ad9783_if.v Executable file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// This is the dac physical interface (drives samples from the low speed clock to the
// dac clock domain.
`timescale 1ns/100ps
module axi_ad9783_if #(
parameter FPGA_TECHNOLOGY = 0) (
// dac interface
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output [15:0] dac_data_out_p,
output [15:0] dac_data_out_n,
// internal resets and clocks
input dac_rst,
output dac_div_clk,
output reg dac_status,
// data interface
input [15:0] dac_data_a0,
input [15:0] dac_data_a1,
input [15:0] dac_data_a2,
input [15:0] dac_data_a3,
input [15:0] dac_data_b0,
input [15:0] dac_data_b1,
input [15:0] dac_data_b2,
input [15:0] dac_data_b3);
// internal registers
// internal signals
wire dac_clk_in_s;
wire dac_div_clk_s;
wire dac_clk_s;
// dac status
always @(posedge dac_div_clk) begin
if (dac_rst == 1'b1) begin
dac_status <= 1'd0;
end else begin
dac_status <= 1'd1;
end
end
// dac data output serdes(s) & buffers
ad_serdes_out #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(16),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_data (
.rst (dac_rst),
.clk (dac_clk_s),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_oe (1'b1),
.data_s0 (dac_data_a0),
.data_s1 (dac_data_b0),
.data_s2 (dac_data_a1),
.data_s3 (dac_data_b1),
.data_s4 (dac_data_a2),
.data_s5 (dac_data_b2),
.data_s6 (dac_data_a3),
.data_s7 (dac_data_b3),
.data_out_se (),
.data_out_p (dac_data_out_p),
.data_out_n (dac_data_out_n));
// dac clock output serdes & buffer
ad_serdes_out #(
.DDR_OR_SDR_N(1),
.DATA_WIDTH(1),
.SERDES_FACTOR(8),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
i_serdes_out_clk (
.rst (dac_rst),
.clk (dac_clk_s),
.div_clk (dac_div_clk),
.loaden (1'b0),
.data_oe (1'b1),
.data_s0 (1'b1),
.data_s1 (1'b0),
.data_s2 (1'b1),
.data_s3 (1'b0),
.data_s4 (1'b1),
.data_s5 (1'b0),
.data_s6 (1'b1),
.data_s7 (1'b0),
.data_out_se (),
.data_out_p (dac_clk_out_p),
.data_out_n (dac_clk_out_n));
// dac clock input buffers
IBUFGDS i_dac_clk_in_ibuf (
.I (dac_clk_in_p),
.IB (dac_clk_in_n),
.O (dac_clk_s));
BUFGCE_DIV #(
.BUFGCE_DIVIDE (4),
.IS_CE_INVERTED (1'b0),
.IS_CLR_INVERTED (1'b0),
.IS_I_INVERTED (1'b0)
) i_dac_div_clk_rbuf (
.O (dac_div_clk_s),
.CE (1'b1),
.CLR (1'b0),
.I (dac_clk_s));
BUFG i_dac_div_clk_gbuf (
.I (dac_div_clk_s),
.O (dac_div_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_ad9783/axi_ad9783_ip.tcl Executable file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ad9783
adi_ip_files axi_ad9783 [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"axi_ad9783_channel.v" \
"axi_ad9783_core.v" \
"axi_ad9783_if.v" \
"axi_ad9783.v" ]
adi_ip_properties axi_ad9783
set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9783} [ipx::current_core]
adi_init_bd_tcl
adi_ip_bd axi_ad9783 "bd/bd.tcl"
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]