diff --git a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
index 144855ec8..45d930c2d 100644
--- a/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
+++ b/library/axi_ad9361/altera/axi_ad9361_lvds_if.v
@@ -150,7 +150,6 @@ module axi_ad9361_lvds_if #(
   reg             txnrx_n_int = 'd0;
   reg             enable_p_int = 'd0;
   reg             txnrx_p_int = 'd0;
-  reg    [47:0]   tx_data_lclk = 'd0;
   reg    [ 5:0]   tx_p_data_d_0 = 'd0;
   reg    [ 5:0]   tx_p_data_d_1 = 'd0;
   reg    [ 5:0]   tx_p_data_d_2 = 'd0;
@@ -498,7 +497,9 @@ module axi_ad9361_lvds_if #(
 
   // serdes clock interface
 
-  ad_serdes_clk ad_serdes_clk (
+  ad_serdes_clk #(
+    .DEVICE_TYPE(DEVICE_TYPE))
+  ad_serdes_clk (
     .rst (mmcm_rst),
     .clk_in_p (rx_clk_in_p),
     .clk_in_n (rx_clk_in_n),
diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl
index 7f2729e29..d8696c7a9 100644
--- a/library/axi_ad9361/axi_ad9361_hw.tcl
+++ b/library/axi_ad9361/axi_ad9361_hw.tcl
@@ -16,12 +16,9 @@ set_module_property ELABORATION_CALLBACK p_axi_ad9361
 add_fileset quartus_synth QUARTUS_SYNTH "" ""
 set_fileset_property quartus_synth TOP_LEVEL axi_ad9361
 add_fileset_file ad_rst.v                 VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
-add_fileset_file ad_lvds_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_clk.v
 add_fileset_file ad_serdes_clk.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_clk.v
 add_fileset_file ad_serdes_in.v           VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_in.v
 add_fileset_file ad_serdes_out.v          VERILOG PATH $ad_hdl_dir/library/altera/common/ad_serdes_out.v
-add_fileset_file ad_lvds_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_in.v
-add_fileset_file ad_lvds_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_lvds_out.v
 add_fileset_file ad_cmos_clk.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_clk.v
 add_fileset_file ad_cmos_in.v             VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_in.v
 add_fileset_file ad_cmos_out.v            VERILOG PATH $ad_hdl_dir/library/altera/common/ad_cmos_out.v