From 08a5e944f000d3e867db953ac7e625af4eaaadca Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 7 Feb 2022 08:22:46 +0000 Subject: [PATCH] cn0577: Initial commit Created a virtual clock to constrain cnv_en. Given that the cnv_en should be asserted only once per 8 clock cycles and only the rise edge is of interest, we can constrain the path as multicycle path. --- projects/cn0577/Makefile | 7 + projects/cn0577/Readme.md | 9 + projects/cn0577/common/cn0577_bd.tcl | 86 ++++++++ projects/cn0577/zed/Makefile | 27 +++ projects/cn0577/zed/system_bd.tcl | 13 ++ projects/cn0577/zed/system_constr.xdc | 72 +++++++ projects/cn0577/zed/system_project.tcl | 14 ++ projects/cn0577/zed/system_top.v | 277 +++++++++++++++++++++++++ 8 files changed, 505 insertions(+) create mode 100644 projects/cn0577/Makefile create mode 100644 projects/cn0577/Readme.md create mode 100644 projects/cn0577/common/cn0577_bd.tcl create mode 100644 projects/cn0577/zed/Makefile create mode 100644 projects/cn0577/zed/system_bd.tcl create mode 100644 projects/cn0577/zed/system_constr.xdc create mode 100644 projects/cn0577/zed/system_project.tcl create mode 100644 projects/cn0577/zed/system_top.v diff --git a/projects/cn0577/Makefile b/projects/cn0577/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/cn0577/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/cn0577/Readme.md b/projects/cn0577/Readme.md new file mode 100644 index 000000000..5b2993482 --- /dev/null +++ b/projects/cn0577/Readme.md @@ -0,0 +1,9 @@ +# CN0577 HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/eval-cn0577) + * Parts: [SAR ADC, LVDS interface, 18-bit resolution, Sample rate up to 15MSPS](https://www.analog.com/ltc2387-18) + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577 + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all + diff --git a/projects/cn0577/common/cn0577_bd.tcl b/projects/cn0577/common/cn0577_bd.tcl new file mode 100644 index 000000000..3273e45e6 --- /dev/null +++ b/projects/cn0577/common/cn0577_bd.tcl @@ -0,0 +1,86 @@ +# ltc2387 + +create_bd_port -dir I ref_clk +create_bd_port -dir O sampling_clk +create_bd_port -dir I dco_p +create_bd_port -dir I dco_n +create_bd_port -dir O cnv +create_bd_port -dir I da_p +create_bd_port -dir I da_n +create_bd_port -dir I db_p +create_bd_port -dir I db_n +create_bd_port -dir O clk_gate + +# adc peripheral + +ad_ip_instance axi_ltc2387 axi_ltc2387 +ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES 18 +ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES 32 +ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $two_lanes +ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27 + +# axi pwm gen + +ad_ip_instance axi_pwm_gen axi_pwm_gen +ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH 5 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 8 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0 + +# dma + +ad_ip_instance axi_dmac axi_ltc2387_dma +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC 32 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +# connections + +ad_connect ref_clk sampling_clk + +ad_connect sys_200m_clk axi_ltc2387/delay_clk + +ad_connect ref_clk axi_ltc2387/ref_clk +ad_connect clk_gate axi_ltc2387/clk_gate +ad_connect dco_p axi_ltc2387/dco_p +ad_connect dco_n axi_ltc2387/dco_n +ad_connect da_n axi_ltc2387/da_n +ad_connect da_p axi_ltc2387/da_p +ad_connect db_n axi_ltc2387/db_n +ad_connect db_p axi_ltc2387/db_p + +ad_connect cnv axi_pwm_gen/pwm_0 +ad_connect clk_gate axi_pwm_gen/pwm_1 + +ad_connect ref_clk axi_pwm_gen/ext_clk +ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn +ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk +ad_connect ref_clk axi_ltc2387_dma/fifo_wr_clk + +ad_connect axi_ltc2387/adc_valid axi_ltc2387_dma/fifo_wr_en +ad_connect axi_ltc2387/adc_data axi_ltc2387_dma/fifo_wr_din +ad_connect axi_ltc2387/adc_dovf axi_ltc2387_dma/fifo_wr_overflow + +# address mapping + +ad_cpu_interconnect 0x44A00000 axi_ltc2387 +ad_cpu_interconnect 0x44A30000 axi_ltc2387_dma +ad_cpu_interconnect 0x44A60000 axi_pwm_gen + +# interconnect (adc) + +ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect $sys_cpu_clk axi_ltc2387_dma/m_dest_axi +ad_connect $sys_cpu_resetn axi_ltc2387_dma/m_dest_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ltc2387_dma/irq diff --git a/projects/cn0577/zed/Makefile b/projects/cn0577/zed/Makefile new file mode 100644 index 000000000..3c78e1c8b --- /dev/null +++ b/projects/cn0577/zed/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := cn0577_zed + +M_DEPS += ../common/cn0577_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_ltc2387 +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/cn0577/zed/system_bd.tcl b/projects/cn0577/zed/system_bd.tcl new file mode 100644 index 000000000..0930be442 --- /dev/null +++ b/projects/cn0577/zed/system_bd.tcl @@ -0,0 +1,13 @@ +# specify number of channels -- the design supports one lane/two lanes +set two_lanes 1 + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source ../common/cn0577_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/cn0577/zed/system_constr.xdc b/projects/cn0577/zed/system_constr.xdc new file mode 100644 index 000000000..0550e21f7 --- /dev/null +++ b/projects/cn0577/zed/system_constr.xdc @@ -0,0 +1,72 @@ + +# cn0577 + +# pin connections + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_p]; #G02 FMC_LPC_CLK1_M2C_P +set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_n]; #G03 FMC_LPC_CLK1_M2C_N +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]; #H04 FMC_LPC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]; #H05 FMC_LPC_CLK0_M2C_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports da_p]; #H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports da_n]; #H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports db_p]; #H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports db_n]; #H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p]; #G06 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n]; #G07 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p]; #D08 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n]; #D09 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports cnv_en]; #G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports pd_cntrl]; #G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports testpat_cntrl]; #G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports twolanes_cntrl]; #G24 FMC_LPC_LA22_P + +# 120MHz clock +set clk_period 8.333 +# differential propagation delay for ref_clk +set tref_early 0.3 +set tref_late 1.5 +# differential propagation delay for virt_clk +set tvirt_early 0 +set tvirt_late 0.225 +# data delay +set data_delay 0.200 + +# clocks + +create_clock -period $clk_period -name dco [get_ports dco_p] +create_clock -period $clk_period -name ref_clk [get_ports ref_clk_p] +create_clock -period $clk_period -name virt_clk + +# clock latencies + +# minimum source latency values +set_clock_latency -source -early $tref_early [get_clocks ref_clk] +set_clock_latency -source -early $tvirt_early [get_clocks virt_clk] +# maximum source latency values +set_clock_latency -source -late $tref_late [get_clocks ref_clk] +set_clock_latency -source -late $tvirt_late [get_clocks virt_clk] + +# input delays + +set_input_delay -clock dco -max $data_delay [get_ports da_p] +set_input_delay -clock dco -min -$data_delay [get_ports da_p] +set_input_delay -clock dco -clock_fall -max -add_delay $data_delay [get_ports da_p] +set_input_delay -clock dco -clock_fall -min -add_delay -$data_delay [get_ports da_p] + +set_input_delay -clock dco -max $data_delay [get_ports db_p] +set_input_delay -clock dco -min -$data_delay [get_ports db_p] +set_input_delay -clock dco -clock_fall -max -add_delay $data_delay [get_ports db_p] +set_input_delay -clock dco -clock_fall -min -add_delay -$data_delay [get_ports db_p] + +# output delays + +set_output_delay -clock [get_clocks virt_clk] -max 2 [get_ports cnv_en] +set_output_delay -clock [get_clocks virt_clk] -min -0.3 [get_ports cnv_en] + +# multicycle paths + +set_multicycle_path 2 -setup -end -from ref_clk -to virt_clk +set_multicycle_path 1 -hold -start -from ref_clk -to virt_clk + +set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_db/i_rx_data_idelay] +set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_da/i_rx_data_idelay] diff --git a/projects/cn0577/zed/system_project.tcl b/projects/cn0577/zed/system_project.tcl new file mode 100644 index 000000000..cad6b3edb --- /dev/null +++ b/projects/cn0577/zed/system_project.tcl @@ -0,0 +1,14 @@ +# load script +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project cn0577_zed +adi_project_files cn0577_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run cn0577_zed diff --git a/projects/cn0577/zed/system_top.v b/projects/cn0577/zed/system_top.v new file mode 100644 index 000000000..0227db9ae --- /dev/null +++ b/projects/cn0577/zed/system_top.v @@ -0,0 +1,277 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2022 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + input ref_clk_p, + input ref_clk_n, + output clk_p, + output clk_n, + input dco_p, + input dco_n, + input da_n, + input da_p, + input db_n, + input db_p, + output cnv_p, + output cnv_n, + output cnv_en, + output pd_cntrl, + output testpat_cntrl, + output twolanes_cntrl +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire clk_s; + wire cnv_s; + wire cnv; + wire clk_gate; + wire sampling_clk_s; + wire ltc_clk; + + assign gpio_i[63:34] = gpio_o[63:34]; + assign twolanes_cntrl = 1'b1; + assign cnv_en = cnv; + + // instantiations + + ad_data_clk #( + .SINGLE_ENDED (0) + ) i_ref_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (ref_clk_p), + .clk_in_n (ref_clk_n), + .clk (clk_s)); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_tx_clk_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (clk_gate), + .D2 (1'b0), + .Q (ltc_clk)); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_cnv_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (cnv), + .D2 (cnv), + .Q (cnv_s)); + + OBUFDS i_tx_data_obuf ( + .I (ltc_clk), + .O (clk_p), + .OB (clk_n)); + + OBUFDS OBUFDS_cnv ( + .O (cnv_p), + .OB (cnv_n), + .I (cnv_s)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) iobuf_gpio_cn0577 ( + .dio_i (gpio_o[33:32]), + .dio_o (gpio_i[33:32]), + .dio_t (gpio_t[33:32]), + .dio_p ({pd_cntrl, testpat_cntrl})); + + ad_iobuf #( + .DATA_WIDTH(32) + ) iobuf_gpio_bd ( + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_t (gpio_t[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .ref_clk (clk_s), + .sampling_clk (sampling_clk_s), + .dco_p (dco_p), + .dco_n (dco_n), + .da_n (da_n), + .da_p (da_p), + .db_n (db_n), + .db_p (db_p), + .cnv (cnv), + .clk_gate (clk_gate), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b0), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b0), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule