From 08977161670f02afaa53a317f482c0cde38142a7 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 14 Nov 2016 15:59:09 +0200 Subject: [PATCH] fmcadc4: xcvr updates --- projects/fmcadc4/common/fmcadc4_bd.tcl | 101 +++++----------------- projects/fmcadc4/zc706/Makefile | 12 +-- projects/fmcadc4/zc706/system_bd.tcl | 36 -------- projects/fmcadc4/zc706/system_constr.xdc | 3 +- projects/fmcadc4/zc706/system_project.tcl | 2 - projects/fmcadc4/zc706/system_top.v | 24 +++-- 6 files changed, 48 insertions(+), 130 deletions(-) diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index c4a910818..5c70a6179 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -1,12 +1,6 @@ # fmcadc4 -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir I rx_sysref -create_bd_port -dir I -from 7 -to 0 rx_data_p -create_bd_port -dir I -from 7 -to 0 rx_data_n - # adc peripherals set axi_ad9680_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_0] @@ -14,6 +8,11 @@ set_property -dict [list CONFIG.ID {0}] $axi_ad9680_core_0 set axi_ad9680_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core_1] set_property -dict [list CONFIG.ID {1}] $axi_ad9680_core_1 +set axi_ad9680_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9680_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9680_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9680_xcvr + set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9680_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9680_jesd @@ -37,22 +36,8 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $axi_ad9680_cpack # adc common gt -set axi_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc4_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc4_gt -set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_fmcadc4_gt - -set util_fmcadc4_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc4_gt] -set_property -dict [list CONFIG.QPLL_TX_OR_RX_N {0}] $util_fmcadc4_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_fmcadc4_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {1}] $util_fmcadc4_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc4_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc4_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc4_gt +set util_fmcadc4_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc4_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc4_xcvr create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_data set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {128}] [get_bd_cells util_bsplit_rx_data] @@ -60,64 +45,19 @@ set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_r # connections (gt) -ad_connect util_fmcadc4_gt/qpll_ref_clk rx_ref_clk - -ad_connect axi_fmcadc4_gt/gt_qpll_0 util_fmcadc4_gt/gt_qpll_0 -ad_connect axi_fmcadc4_gt/gt_qpll_1 util_fmcadc4_gt/gt_qpll_1 -ad_connect axi_fmcadc4_gt/gt_pll_0 util_fmcadc4_gt/gt_pll_0 -ad_connect axi_fmcadc4_gt/gt_pll_1 util_fmcadc4_gt/gt_pll_1 -ad_connect axi_fmcadc4_gt/gt_pll_2 util_fmcadc4_gt/gt_pll_2 -ad_connect axi_fmcadc4_gt/gt_pll_3 util_fmcadc4_gt/gt_pll_3 -ad_connect axi_fmcadc4_gt/gt_pll_4 util_fmcadc4_gt/gt_pll_4 -ad_connect axi_fmcadc4_gt/gt_pll_5 util_fmcadc4_gt/gt_pll_5 -ad_connect axi_fmcadc4_gt/gt_pll_6 util_fmcadc4_gt/gt_pll_6 -ad_connect axi_fmcadc4_gt/gt_pll_7 util_fmcadc4_gt/gt_pll_7 -ad_connect axi_fmcadc4_gt/gt_rx_0 util_fmcadc4_gt/gt_rx_0 -ad_connect axi_fmcadc4_gt/gt_rx_1 util_fmcadc4_gt/gt_rx_1 -ad_connect axi_fmcadc4_gt/gt_rx_2 util_fmcadc4_gt/gt_rx_2 -ad_connect axi_fmcadc4_gt/gt_rx_3 util_fmcadc4_gt/gt_rx_3 -ad_connect axi_fmcadc4_gt/gt_rx_4 util_fmcadc4_gt/gt_rx_4 -ad_connect axi_fmcadc4_gt/gt_rx_5 util_fmcadc4_gt/gt_rx_5 -ad_connect axi_fmcadc4_gt/gt_rx_6 util_fmcadc4_gt/gt_rx_6 -ad_connect axi_fmcadc4_gt/gt_rx_7 util_fmcadc4_gt/gt_rx_7 -ad_connect axi_fmcadc4_gt/gt_rx_ip_0 axi_ad9680_jesd/gt0_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_1 axi_ad9680_jesd/gt1_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_2 axi_ad9680_jesd/gt2_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_3 axi_ad9680_jesd/gt3_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_4 axi_ad9680_jesd/gt4_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_5 axi_ad9680_jesd/gt5_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_6 axi_ad9680_jesd/gt6_rx -ad_connect axi_fmcadc4_gt/gt_rx_ip_7 axi_ad9680_jesd/gt7_rx -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_0 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_1 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_2 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_3 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_4 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_5 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_6 axi_ad9680_jesd/rxencommaalign_out -ad_connect axi_fmcadc4_gt/rx_gt_comma_align_enb_7 axi_ad9680_jesd/rxencommaalign_out +ad_xcvrcon util_fmcadc4_xcvr axi_ad9680_xcvr axi_ad9680_jesd +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_cpack/adc_clk +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_0/rx_clk +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_core_1/rx_clk +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_0/rx_sof +ad_connect axi_ad9680_jesd/rx_start_of_frame axi_ad9680_core_1/rx_sof +ad_connect axi_ad9680_jesd/rx_tdata util_bsplit_rx_data/data +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_cpack/adc_rst # connections (adc) -ad_connect util_fmcadc4_gt/rx_p rx_data_p -ad_connect util_fmcadc4_gt/rx_n rx_data_n -ad_connect util_fmcadc4_gt/rx_sysref rx_sysref -ad_connect util_fmcadc4_gt/rx_sync rx_sync -ad_connect util_fmcadc4_gt/rx_out_clk util_fmcadc4_gt/rx_clk -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_jesd/rx_core_clk -ad_connect util_fmcadc4_gt/rx_ip_rst axi_ad9680_jesd/rx_reset -ad_connect util_fmcadc4_gt/rx_ip_rst_done axi_ad9680_jesd/rx_reset_done -ad_connect util_fmcadc4_gt/rx_ip_sysref axi_ad9680_jesd/rx_sysref -ad_connect util_fmcadc4_gt/rx_ip_sync axi_ad9680_jesd/rx_sync -ad_connect util_fmcadc4_gt/rx_ip_sof axi_ad9680_jesd/rx_start_of_frame -ad_connect util_fmcadc4_gt/rx_ip_data axi_ad9680_jesd/rx_tdata -ad_connect util_fmcadc4_gt/rx_data util_bsplit_rx_data/data -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_0/rx_clk -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_core_1/rx_clk ad_connect util_bsplit_rx_data/split_data_0 axi_ad9680_core_0/rx_data ad_connect util_bsplit_rx_data/split_data_1 axi_ad9680_core_1/rx_data -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_cpack/adc_clk -ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_cpack/adc_rst ad_connect axi_ad9680_core_0/adc_enable_0 axi_ad9680_cpack/adc_enable_0 ad_connect axi_ad9680_core_0/adc_valid_0 axi_ad9680_cpack/adc_valid_0 ad_connect axi_ad9680_core_0/adc_data_0 axi_ad9680_cpack/adc_data_0 @@ -130,8 +70,8 @@ ad_connect axi_ad9680_core_1/adc_data_0 axi_ad9680_cpack/adc_data_2 ad_connect axi_ad9680_core_1/adc_enable_1 axi_ad9680_cpack/adc_enable_3 ad_connect axi_ad9680_core_1/adc_valid_1 axi_ad9680_cpack/adc_valid_3 ad_connect axi_ad9680_core_1/adc_data_1 axi_ad9680_cpack/adc_data_3 -ad_connect util_fmcadc4_gt/rx_out_clk axi_ad9680_fifo/adc_clk -ad_connect util_fmcadc4_gt/rx_rst axi_ad9680_fifo/adc_rst +ad_connect util_fmcadc4_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk +ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk @@ -143,9 +83,12 @@ ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req ad_connect axi_ad9680_core_0/adc_dovf axi_ad9680_fifo/adc_wovf +ad_connect sys_cpu_clk util_fmcadc4_xcvr/up_clk +ad_connect sys_cpu_resetn util_fmcadc4_xcvr/up_rstn + # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_fmcadc4_gt +ad_cpu_interconnect 0x44A60000 axi_ad9680_xcvr ad_cpu_interconnect 0x44A00000 axi_ad9680_core_0 ad_cpu_interconnect 0x44A10000 axi_ad9680_core_1 ad_cpu_interconnect 0x44A91000 axi_ad9680_jesd @@ -154,7 +97,7 @@ ad_cpu_interconnect 0x7c400000 axi_ad9680_dma # gt uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_fmcadc4_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/adc) diff --git a/projects/fmcadc4/zc706/Makefile b/projects/fmcadc4/zc706/Makefile index e939d348d..82a79c8d5 100644 --- a/projects/fmcadc4/zc706/Makefile +++ b/projects/fmcadc4/zc706/Makefile @@ -22,14 +22,14 @@ M_DEPS += ../../common/zc706/zc706_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9680/axi_ad9680.xpr M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_DEPS += ../../../library/util_mfifo/util_mfifo.xpr M_VIVADO := vivado -mode batch -source @@ -61,14 +61,14 @@ clean: clean-all:clean make -C ../../../library/axi_ad9680 clean make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_bsplit clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean make -C ../../../library/util_mfifo clean @@ -80,14 +80,14 @@ fmcadc4_zc706.sdk/system_top.hdf: $(M_DEPS) lib: make -C ../../../library/axi_ad9680 make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_bsplit make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt make -C ../../../library/util_mfifo #################################################################################### diff --git a/projects/fmcadc4/zc706/system_bd.tcl b/projects/fmcadc4/zc706/system_bd.tcl index 59392004d..91e5cfa22 100644 --- a/projects/fmcadc4/zc706/system_bd.tcl +++ b/projects/fmcadc4/zc706/system_bd.tcl @@ -20,39 +20,3 @@ create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \ SEG_axi_ddr_cntrl_memaddr source ../common/fmcadc4_bd.tcl - -# ila - -set mfifo_adc [create_bd_cell -type ip -vlnv analog.com:user:util_mfifo:1.0 mfifo_adc] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $mfifo_adc -set_property -dict [list CONFIG.DIN_DATA_WIDTH {64}] $mfifo_adc -set_property -dict [list CONFIG.ADDRESS_WIDTH {8}] $mfifo_adc - -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc -set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc - -ad_connect util_fmcadc4_gt/rx_rst mfifo_adc/din_rst -ad_connect util_fmcadc4_gt/rx_out_clk mfifo_adc/din_clk -ad_connect axi_ad9680_core_0/adc_valid_0 mfifo_adc/din_valid -ad_connect axi_ad9680_core_0/adc_data_0 mfifo_adc/din_data_0 -ad_connect axi_ad9680_core_0/adc_data_1 mfifo_adc/din_data_1 -ad_connect axi_ad9680_core_1/adc_data_0 mfifo_adc/din_data_2 -ad_connect axi_ad9680_core_1/adc_data_1 mfifo_adc/din_data_3 -ad_connect util_fmcadc4_gt/rx_rst mfifo_adc/dout_rst -ad_connect util_fmcadc4_gt/rx_out_clk mfifo_adc/dout_clk -ad_connect util_fmcadc4_gt/rx_out_clk ila_adc/clk -ad_connect mfifo_adc/dout_valid ila_adc/probe0 -ad_connect mfifo_adc/dout_data_0 ila_adc/probe1 -ad_connect mfifo_adc/dout_data_1 ila_adc/probe2 -ad_connect mfifo_adc/dout_data_2 ila_adc/probe3 -ad_connect mfifo_adc/dout_data_3 ila_adc/probe4 - - diff --git a/projects/fmcadc4/zc706/system_constr.xdc b/projects/fmcadc4/zc706/system_constr.xdc index 4f8607ec8..a3486e1e2 100644 --- a/projects/fmcadc4/zc706/system_constr.xdc +++ b/projects/fmcadc4/zc706/system_constr.xdc @@ -46,5 +46,4 @@ set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9680_2 # clocks create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_fmcadc4_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] - +create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_fmcadc4_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/fmcadc4/zc706/system_project.tcl b/projects/fmcadc4/zc706/system_project.tcl index 787434877..63fe133b5 100644 --- a/projects/fmcadc4/zc706/system_project.tcl +++ b/projects/fmcadc4/zc706/system_project.tcl @@ -14,8 +14,6 @@ adi_project_files fmcadc4_zc706 [list \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc] - adi_project_run fmcadc4_zc706 diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v index 77be2f7b0..2f89d49b9 100644 --- a/projects/fmcadc4/zc706/system_top.v +++ b/projects/fmcadc4/zc706/system_top.v @@ -345,11 +345,25 @@ module system_top ( .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_12 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk),