From 08777ca5667b69a38e441ed04fac7dd11d3d00fc Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 15 Oct 2015 10:45:46 -0400 Subject: [PATCH] fmcadc5- latest board changes --- projects/fmcadc5/vc707/system_constr.xdc | 5 ++- projects/fmcadc5/vc707/system_project.tcl | 1 + projects/fmcadc5/vc707/system_top.v | 47 ++++++++++++++--------- 3 files changed, 33 insertions(+), 20 deletions(-) diff --git a/projects/fmcadc5/vc707/system_constr.xdc b/projects/fmcadc5/vc707/system_constr.xdc index 87c6816d2..cb5b15068 100644 --- a/projects/fmcadc5/vc707/system_constr.xdc +++ b/projects/fmcadc5/vc707/system_constr.xdc @@ -77,9 +77,12 @@ set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVCMOS18} [get_ports dac_data set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVCMOS18} [get_ports dac_sync_0] ; ## C18 FMC1_HPC_LA14_P set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVCMOS18} [get_ports dac_sync_1] ; ## C19 FMC1_HPC_LA14_N +set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVCMOS18} [get_ports psync_0] ; ## G15 FMC1_HPC_LA12_P +set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVCMOS18} [get_ports psync_1] ; ## G16 FMC1_HPC_LA12_N + # clocks create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p] create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p] -create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9625_0_gt/inst/g_lane_1[0].i_gt_channel_1/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_fmcadc5_0_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/fmcadc5/vc707/system_project.tcl b/projects/fmcadc5/vc707/system_project.tcl index bc693ca3a..5a30f0193 100644 --- a/projects/fmcadc5/vc707/system_project.tcl +++ b/projects/fmcadc5/vc707/system_project.tcl @@ -8,6 +8,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcadc5_vc707 adi_project_files fmcadc5_vc707 [list \ "../common/fmcadc5_spi.v" \ + "../common/fmcadc5_psync.v" \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ diff --git a/projects/fmcadc5/vc707/system_top.v b/projects/fmcadc5/vc707/system_top.v index 9946cd264..8801e44d0 100644 --- a/projects/fmcadc5/vc707/system_top.v +++ b/projects/fmcadc5/vc707/system_top.v @@ -112,6 +112,8 @@ module system_top ( spi_sdio, spi_dirn, + psync_0, + psync_1, trig_p, trig_n, vdither_p, @@ -209,6 +211,8 @@ module system_top ( output dac_sync_0; output dac_sync_1; + output psync_0; + output psync_1; input trig_p; input trig_n; output vdither_p; @@ -220,17 +224,12 @@ module system_top ( inout irq_0; inout pwdn_1; inout rst_1; - inout drst_1; - inout arst_1; + output drst_1; + output arst_1; inout pwdn_0; inout rst_0; - inout drst_0; - inout arst_0; - - // internal registers - - reg adc_wr = 'd0; - reg [511:0] adc_wdata = 'd0; + output drst_0; + output arst_0; // internal signals @@ -246,6 +245,8 @@ module system_top ( wire rx_sysref; wire rx_sync_0; wire rx_sync_1; + wire up_rstn; + wire up_clk; // spi @@ -257,6 +258,10 @@ module system_top ( assign dac_sync_0 = spi_csn[2]; assign spi_csn_1 = spi_csn[1]; assign spi_csn_0 = spi_csn[0]; + assign drst_1 = 1'b0; + assign arst_1 = 1'b0; + assign drst_0 = 1'b0; + assign arst_0 = 1'b0; // instantiations @@ -299,6 +304,12 @@ module system_top ( .O (vdither_p), .OB (vdither_n)); + fmcadc5_psync i_fmcadc5_psync ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .psync_0 (psync_0), + .psync_1 (psync_1)); + fmcadc5_spi i_fmcadc5_spi ( .spi_csn_0 (spi_csn_0), .spi_csn_1 (spi_csn_1), @@ -308,10 +319,10 @@ module system_top ( .spi_sdio (spi_sdio), .spi_dirn (spi_dirn)); - ad_iobuf #(.DATA_WIDTH(13)) i_iobuf ( - .dio_t (gpio_t[44:32]), - .dio_i (gpio_o[44:32]), - .dio_o (gpio_i[44:32]), + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf ( + .dio_t ({gpio_t[44:40], gpio_t[39:38], gpio_t[35:34]}), + .dio_i ({gpio_o[44:40], gpio_o[39:38], gpio_o[35:34]}), + .dio_o ({gpio_i[44:40], gpio_i[39:38], gpio_i[35:34]}), .dio_p ({ pwr_good, // 44 fd_1, // 43 irq_1, // 42 @@ -319,12 +330,8 @@ module system_top ( irq_0, // 40 pwdn_1, // 39 rst_1, // 38 - drst_1, // 37 - arst_1, // 36 pwdn_0, // 35 - rst_0, // 34 - drst_0, // 33 - arst_0})); // 32 + rst_0})); // 34 ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd ( .dio_t (gpio_t[20:0]), @@ -399,7 +406,9 @@ module system_top ( .sys_clk_p (sys_clk_p), .sys_rst (sys_rst), .uart_sin (uart_sin), - .uart_sout (uart_sout)); + .uart_sout (uart_sout), + .up_clk (up_clk), + .up_rstn (up_rstn)); endmodule