From 083962450a41c4ad976679111907297aa964edc8 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 19 Oct 2017 16:07:18 +0300 Subject: [PATCH] daq2: A10GX, connect dac_fifo_bypass to gpio --- projects/daq2/a10gx/system_top.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v index 258c60ab1..e6e91e21b 100644 --- a/projects/daq2/a10gx/system_top.v +++ b/projects/daq2/a10gx/system_top.v @@ -131,6 +131,7 @@ module system_top ( wire spi_miso_s; wire spi_mosi_s; wire [ 7:0] spi_csn_s; + wire dac_fifo_bypass; // User code space at offset 0x0930_0000 per Altera's Board Update Portal // reference design used to program flash @@ -155,6 +156,7 @@ module system_top ( // gpio in & out are separate cores assign gpio_i[63:44] = gpio_o[63:44]; + assign dac_fifo_bypass = gpio_o[44]; assign gpio_i[43:43] = trig; assign gpio_i[42:40] = gpio_o[42:40]; @@ -236,6 +238,7 @@ module system_top ( .sys_spi_SCLK (spi_clk), .sys_spi_SS_n (spi_csn_s), .tx_serial_data_tx_serial_data (tx_serial_data), + .tx_fifo_bypass_bypass (dac_fifo_bypass), .tx_ref_clk_clk (tx_ref_clk), .tx_sync_export (tx_sync), .tx_sysref_export (tx_sysref),