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library/jesd204: tpl timing bug fix

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Filip Gherman 2021-12-21 20:29:09 +02:00 committed by Filip Gherman
parent 3d000ee6a8
commit 080925e8fe
1 changed files with 8 additions and 1 deletions
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9
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
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@ -66,16 +66,23 @@ module ad_ip_jesd204_tpl_adc_core #(
localparam CDW_FMT = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH; localparam CDW_FMT = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH;
wire [ADC_DATA_WIDTH-1:0] raw_data_s; wire [ADC_DATA_WIDTH-1:0] raw_data_s;
wire link_valid_tmp;
reg adc_sync_armed = 1'b0; reg adc_sync_armed = 1'b0;
reg adc_sync_in_d1 = 1'b0; reg adc_sync_in_d1 = 1'b0;
reg adc_sync_d1 = 1'b0; reg adc_sync_d1 = 1'b0;
reg link_valid_d = 1'b0;
assign link_ready = 1'b1; assign link_ready = 1'b1;
assign adc_valid = {NUM_CHANNELS{link_valid}}; assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_d : link_valid;
assign adc_valid = {NUM_CHANNELS{link_valid_tmp}};
assign adc_sync_status = adc_sync_armed; assign adc_sync_status = adc_sync_armed;
assign adc_rst_sync = adc_sync_armed; assign adc_rst_sync = adc_sync_armed;
always @(posedge clk) begin
link_valid_d <= link_valid;
end
always @(posedge clk) begin always @(posedge clk) begin
adc_sync_in_d1 <= adc_sync_in; adc_sync_in_d1 <= adc_sync_in;
adc_sync_d1 <= adc_sync; adc_sync_d1 <= adc_sync;