library: Add link to wiki for IPs

2021-10-20 16:08:35 +01:00 · 2021-10-20 16:08:35 +01:00 · 076e81a17c
parent 15a6480601
commit 076e81a17c
38 changed files with 77 additions and 0 deletions
--- a/library/axi_ad7616/axi_ad7616_ip.tcl
+++ b/library/axi_ad7616/axi_ad7616_ip.tcl
@ -14,6 +14,8 @@ adi_ip_files axi_ad7616 [list \

 adi_ip_properties axi_ad7616

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7616} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
    analog.com:user:spi_engine_execution:1.0 \
    analog.com:user:axi_spi_engine:1.0 \
--- a/library/axi_ad9144/axi_ad9144_ip.tcl
+++ b/library/axi_ad9144/axi_ad9144_ip.tcl
@ -12,6 +12,8 @@ adi_ip_properties axi_ad9144
 adi_init_bd_tcl
 adi_ip_bd axi_ad9144 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9144} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
  analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
 }
--- a/library/axi_ad9265/axi_ad9265_ip.tcl
+++ b/library/axi_ad9265/axi_ad9265_ip.tcl
@ -32,6 +32,8 @@ adi_ip_properties axi_ad9265
 adi_init_bd_tcl
 adi_ip_bd axi_ad9265 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9265} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

 ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
--- a/library/axi_ad9361/axi_ad9361_ip.tcl
+++ b/library/axi_ad9361/axi_ad9361_ip.tcl
@ -56,6 +56,8 @@ adi_ip_ttcl axi_ad9361 "../common/ad_pps_receiver_constr.ttcl"
 adi_init_bd_tcl
 adi_ip_bd axi_ad9361 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9361} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]]
--- a/library/axi_ad9371/axi_ad9371_ip.tcl
+++ b/library/axi_ad9371/axi_ad9371_ip.tcl
@ -42,6 +42,8 @@ adi_ip_properties axi_ad9371
 adi_init_bd_tcl
 adi_ip_bd axi_ad9371 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9371} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
--- a/library/axi_ad9467/axi_ad9467_ip.tcl
+++ b/library/axi_ad9467/axi_ad9467_ip.tcl
@ -31,6 +31,8 @@ adi_ip_properties axi_ad9467
 adi_init_bd_tcl
 adi_ip_bd axi_ad9467 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9467} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]

 ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
--- a/library/axi_ad9671/axi_ad9671_ip.tcl
+++ b/library/axi_ad9671/axi_ad9671_ip.tcl
@ -30,6 +30,8 @@ adi_ip_properties axi_ad9671
 adi_init_bd_tcl
 adi_ip_bd axi_ad9371 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9671} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]
--- a/library/axi_ad9963/axi_ad9963_ip.tcl
+++ b/library/axi_ad9963/axi_ad9963_ip.tcl
@ -45,6 +45,8 @@ adi_ip_properties axi_ad9963
 adi_init_bd_tcl
 adi_ip_bd axi_ad9963 "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9963} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
--- a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl
+++ b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl
@ -18,6 +18,8 @@ adi_ip_files axi_adc_decimate [list \

 adi_ip_properties axi_adc_decimate

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_decimate} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
  analog.com:user:util_cic:1.0 \
 }
--- a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl
+++ b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl
@ -14,6 +14,8 @@ adi_ip_files axi_adc_trigger [list \

 adi_ip_properties axi_adc_trigger

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_trigger} [ipx::current_core]
+
 ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]

--- a/library/axi_clkgen/axi_clkgen_ip.tcl
+++ b/library/axi_clkgen/axi_clkgen_ip.tcl
@ -16,6 +16,8 @@ adi_ip_files axi_clkgen [list \
 adi_ip_properties axi_clkgen
 adi_ip_bd axi_clkgen "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_clkgen} [ipx::current_core]
+
 ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
--- a/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl
@ -19,6 +19,8 @@ adi_ip_files axi_dac_interpolate [list \

 adi_ip_properties axi_dac_interpolate

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate} [ipx::current_core]
+
 ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]

--- a/library/axi_dmac/axi_dmac_ip.tcl
+++ b/library/axi_dmac/axi_dmac_ip.tcl
@ -43,6 +43,8 @@ adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
 adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl"
 adi_ip_bd axi_dmac "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dmac} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
 	analog.com:user:util_axis_fifo:1.0 \
 	analog.com:user:util_cdc:1.0 \
--- a/library/axi_fan_control/axi_fan_control_ip.tcl
+++ b/library/axi_fan_control/axi_fan_control_ip.tcl
@ -10,6 +10,9 @@ adi_ip_files axi_fan_control [list \
  "axi_fan_control.v"]

 adi_ip_properties axi_fan_control
+
+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_fan_control} [ipx::current_core]
+
 set cc [ipx::current_core]

 ipx::save_core $cc
--- a/library/axi_generic_adc/axi_generic_adc_ip.tcl
+++ b/library/axi_generic_adc/axi_generic_adc_ip.tcl
@ -18,6 +18,8 @@ adi_ip_files axi_generic_adc [list \

 adi_ip_properties axi_generic_adc

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_ip} [ipx::current_core]
+
 ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

 ipx::save_core [ipx::current_core]
--- a/library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
+++ b/library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
@ -25,6 +25,8 @@ adi_ip_files axi_hdmi_rx [list \

 adi_ip_properties axi_hdmi_rx

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_hdmi_rx} [ipx::current_core]
+
 ipx::infer_bus_interface hdmi_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

--- a/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
+++ b/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
@ -31,6 +31,8 @@ adi_ip_properties axi_hdmi_tx
 adi_init_bd_tcl
 adi_ip_bd axi_hdmi_tx "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_hdmi_tx} [ipx::current_core]
+
 set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]]
--- a/library/axi_laser_driver/axi_laser_driver_ip.tcl
+++ b/library/axi_laser_driver/axi_laser_driver_ip.tcl
@ -14,6 +14,8 @@ adi_ip_files axi_laser_driver [list \
 adi_ip_properties axi_laser_driver
 adi_ip_ttcl axi_laser_driver "../axi_pulse_gen/axi_pulse_gen_constr.ttcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_laser_driver} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
 	analog.com:user:util_cdc:1.0 \
 	analog.com:user:axi_pulse_gen:1.0 \
--- a/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
@ -19,6 +19,8 @@ adi_ip_files axi_logic_analyzer [list \

 adi_ip_properties axi_logic_analyzer

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_logic_analyzer} [ipx::current_core]
+
 ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

--- a/library/axi_pwm_gen/axi_pwm_gen_ip.tcl
+++ b/library/axi_pwm_gen/axi_pwm_gen_ip.tcl
@ -16,6 +16,8 @@ adi_ip_files axi_pwm_gen [list \
 adi_ip_properties axi_pwm_gen
 adi_ip_ttcl axi_pwm_gen "axi_pwm_gen_constr.ttcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
 	analog.com:user:util_cdc:1.0 \
 }
--- a/library/axi_sysid/axi_sysid_ip.tcl
+++ b/library/axi_sysid/axi_sysid_ip.tcl
@ -9,6 +9,9 @@ adi_ip_files axi_sysid [list \
  "axi_sysid.v"]

 adi_ip_properties axi_sysid
+
+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_sysid} [ipx::current_core]
+
 set cc [ipx::current_core]

 ipx::save_core $cc
--- a/library/axi_tdd/axi_tdd_ip.tcl
+++ b/library/axi_tdd/axi_tdd_ip.tcl
@ -19,6 +19,7 @@ adi_ip_files axi_tdd [list \
 adi_ip_properties axi_tdd
 set_property display_name "ADI AXI TDD Controller" [ipx::current_core]
 set_property description "ADI AXI TDD Controller" [ipx::current_core]
+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_tdd} [ipx::current_core]

 adi_init_bd_tcl

--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
@ -55,6 +55,8 @@ adi_ip_properties ad_ip_jesd204_tpl_adc
 adi_init_bd_tcl
 adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc} [ipx::current_core]
+
 set cc [ipx::current_core]

 set_property display_name "JESD204 Transport Layer for ADCs" $cc
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
@ -61,6 +61,8 @@ adi_ip_properties ad_ip_jesd204_tpl_dac
 adi_init_bd_tcl
 adi_ip_bd ad_ip_jesd204_tpl_dac "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac} [ipx::current_core]
+
 set cc [ipx::current_core]

 set_property display_name "JESD204 Transport Layer for DACs" $cc
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
@ -60,6 +60,8 @@ adi_ip_properties axi_jesd204_rx

 adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx} [ipx::current_core]
+
 set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
  -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
  -filter {NAME =~ *synthesis*}]]
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
@ -58,6 +58,8 @@ adi_ip_properties axi_jesd204_tx

 adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx} [ipx::current_core]
+
 set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \
  -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
  -filter {NAME =~ *synthesis*}]]
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
@ -20,6 +20,8 @@ adi_ip_add_core_dependencies { \
 	analog.com:user:util_cdc:1.0 \
 }

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi} [ipx::current_core]
+
 ## Interface definitions

 adi_add_bus "spi_engine_ctrl" "master" \
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
@ -10,6 +10,9 @@ adi_ip_files spi_engine_execution [list \

 adi_ip_properties_lite spi_engine_execution
 adi_ip_ttcl spi_engine_execution "spi_engine_execution_constr.ttcl"
+
+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine} [ipx::current_core]
+
 # Remove all inferred interfaces
 ipx::remove_all_bus_interface [ipx::current_core]

--- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl
+++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl
@ -9,6 +9,8 @@ adi_ip_files spi_engine_interconnect [list \

 adi_ip_properties_lite spi_engine_interconnect

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect} [ipx::current_core]
+
 # Remove all inferred interfaces
 ipx::remove_all_bus_interface [ipx::current_core]

--- a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
@ -10,6 +10,8 @@ adi_ip_files spi_engine_offload [list \
 adi_ip_properties_lite spi_engine_offload
 adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload} [ipx::current_core]
+
 # Remove all inferred interfaces
 ipx::remove_all_bus_interface [ipx::current_core]

--- a/library/util_axis_fifo/util_axis_fifo_ip.tcl
+++ b/library/util_axis_fifo/util_axis_fifo_ip.tcl
@ -18,6 +18,7 @@ adi_ip_add_core_dependencies { \

 set_property display_name "ADI AXI Stream FIFO" [ipx::current_core]
 set_property description  "ADI AXI Stream FIFO" [ipx::current_core]
+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo} [ipx::current_core]

 ## Interface definitions

--- a/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
+++ b/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
@ -9,6 +9,8 @@ adi_ip_files util_axis_fifo_asym [list \

 adi_ip_properties_lite util_axis_fifo_asym

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
 	analog.com:user:util_cdc:1.0 \
 	analog.com:user:util_axis_fifo:1.0 \
--- a/library/util_extract/util_extract_ip.tcl
+++ b/library/util_extract/util_extract_ip.tcl
@ -9,6 +9,8 @@ adi_ip_files util_extract [list \

 adi_ip_properties_lite util_extract

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_extract} [ipx::current_core]
+
 ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

 ipx::save_core [ipx::current_core]
--- a/library/util_rfifo/util_rfifo_ip.tcl
+++ b/library/util_rfifo/util_rfifo_ip.tcl
@ -11,6 +11,8 @@ adi_ip_files util_rfifo [list \

 adi_ip_properties_lite util_rfifo

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_rfifo} [ipx::current_core]
+
 ipx::remove_all_bus_interface [ipx::current_core]
 set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]]
--- a/library/util_var_fifo/util_var_fifo_ip.tcl
+++ b/library/util_var_fifo/util_var_fifo_ip.tcl
@ -9,6 +9,8 @@ adi_ip_files util_var_fifo [list \

 adi_ip_properties_lite util_var_fifo

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_var_fifo} [ipx::current_core]
+
 ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]

--- a/library/util_wfifo/util_wfifo_ip.tcl
+++ b/library/util_wfifo/util_wfifo_ip.tcl
@ -11,6 +11,8 @@ adi_ip_files util_wfifo [list \

 adi_ip_properties_lite util_wfifo

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_wfifo} [ipx::current_core]
+
 ipx::remove_all_bus_interface [ipx::current_core]
 set_property driver_value 0 [ipx::get_ports *din_enable* -of_objects [ipx::current_core]]
 set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]]
--- a/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
+++ b/library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
@ -19,6 +19,8 @@ adi_ip_infer_mm_interfaces axi_adxcvr
 adi_init_bd_tcl
 adi_ip_bd axi_adxcvr "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adxcvr} [ipx::current_core]
+
 set cc [ipx::current_core]

 # Arrange GUI page layout
--- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
@ -17,6 +17,8 @@ adi_ip_properties_lite util_adxcvr

 adi_ip_bd util_adxcvr "bd/bd.tcl"

+set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_xcvr} [ipx::current_core]
+
 adi_ip_add_core_dependencies { \
 	analog.com:user:util_cdc:1.0 \
 }