cn0363: Update IP instantiations
Istvan Csomortani
parent
fa794520fd
commit
073718315a
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@ -17,26 +17,24 @@ proc load_fir_filter_vector {filter_file} {
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return $filter
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}
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
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ad_ip_parameter CONFIG.PCW_GPIO_EMIO_GPIO_IO 35
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set_property LEFT 34 [get_bd_ports GPIO_I]
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set_property LEFT 34 [get_bd_ports GPIO_O]
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set_property LEFT 34 [get_bd_ports GPIO_T]
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set axi_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_dma]
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set_property -dict [list \
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CONFIG.FIFO_SIZE 2 \
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CONFIG.DMA_TYPE_SRC 2 \
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CONFIG.DMA_TYPE_DEST 0 \
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CONFIG.CYCLIC 0 \
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CONFIG.SYNC_TRANSFER_START 1 \
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CONFIG.AXI_SLICE_SRC 0 \
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CONFIG.AXI_SLICE_DEST 0 \
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CONFIG.DMA_2D_TRANSFER 0 \
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CONFIG.DMA_DATA_WIDTH_SRC 32 \
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CONFIG.DMA_DATA_WIDTH_DEST 64 \
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CONFIG.DMA_AXI_PROTOCOL_DEST 1 \
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] $axi_dma
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ad_ip_instance axi_dmac axi_dma
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ad_ip_parameter axi_dma CONFIG.FIFO_SIZE 2
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ad_ip_parameter axi_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_dma CONFIG.DMA_DATA_WIDTH_SRC 32
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ad_ip_parameter axi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_ip_parameter axi_dma CONFIG.DMA_AXI_PROTOCOL_DEST 1
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# Create SPI engine controller with offload
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create_bd_cell -type hier spi
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@ -49,15 +47,15 @@ current_bd_instance /spi
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
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set spi_engine [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_execution:1.0 execution]
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set axi_spi_engine [create_bd_cell -type ip -vlnv analog.com:user:axi_spi_engine:1.0 axi]
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set spi_engine_offload [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_offload:1.0 offload]
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set spi_engine_interconnect [create_bd_cell -type ip -vlnv analog.com:user:spi_engine_interconnect:1.0 interconnect]
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set util_sigma_delta_spi [create_bd_cell -type ip -vlnv analog.com:user:util_sigma_delta_spi:1.0 util_sigma_delta_spi]
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ad_ip_instance spi_engine_execution execution
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ad_ip_instance axi_spi_engine axi
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ad_ip_instance spi_engine_offload offload
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ad_ip_instance spi_engine_interconnect interconnect
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ad_ip_instance util_sigma_delta_spi util_sigma_delta_spi
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set_property -dict [list CONFIG.NUM_OF_CS 2] $spi_engine
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ad_ip_parameter spi_engine CONFIG.NUM_OF_CS 2
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set_property -dict [list CONFIG.NUM_OF_CS 2] $util_sigma_delta_spi
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ad_ip_parameter util_sigma_delta_spi CONFIG.NUM_OF_CS 2
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ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
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ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
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@ -97,22 +95,18 @@ current_bd_instance /
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi
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ad_connect spi/m_spi spi
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set phase_gen [create_bd_cell -type ip -vlnv xilinx.com:ip:c_counter_binary:12.0 phase_gen]
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set phase_slice [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 phase_slice]
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ad_ip_instance c_counter_binary phase_gen
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ad_ip_instance xlslice phase_slice
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create_bd_port -dir O excitation
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set excitation_freq 1020
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set_property -dict [list \
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CONFIG.Output_Width 32 \
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CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]] \
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] $phase_gen
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ad_ip_parameter phase_gen CONFIG.Output_Width 32
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ad_ip_parameter phase_gen CONFIG.Increment_Value [format "%x" [expr $excitation_freq * (1<<32) / 100000000]]
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set_property -dict [list \
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CONFIG.DIN_TO {31} \
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CONFIG.DIN_FROM {31} \
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CONFIG.DOUT_WIDTH {1} \
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] $phase_slice
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ad_ip_parameter phase_slice CONFIG.DIN_TO 31
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ad_ip_parameter phase_slice CONFIG.DIN_FROM 31
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ad_ip_parameter phase_slice CONFIG.DOUT_WIDTH 1
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ad_connect /phase_gen/Q /phase_slice/Din
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ad_connect /phase_slice/Dout excitation
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@ -129,64 +123,56 @@ current_bd_instance /processing
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_SAMPLE
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create_bd_intf_pin -mode Master -vlnv analog.com:interface:fifo_wr_rtl:1.0 DMA_WR
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create_bd_cell -type ip -vlnv analog.com:user:cn0363_phase_data_sync:1.0 phase_data_sync
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create_bd_cell -type ip -vlnv analog.com:user:cn0363_dma_sequencer:1.0 sequencer
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create_bd_cell -type ip -vlnv analog.com:user:cordic_demod:1.0 cordic_demod
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ad_ip_instance cn0363_phase_data_sync phase_data_syn
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ad_ip_instance cn0363_dma_sequencer sequence
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ad_ip_instance cordic_demod cordic_demo
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 phase_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 sample_filtered_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 i_q_broadcast
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create_bd_cell -type ip -vlnv xilinx.com:ip:axis_combiner:1.1 phase_sample_combine
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set i_q_resize [create_bd_cell -type ip -vlnv analog.com:user:util_axis_resize:1.0 i_q_resize]
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ad_ip_instance axis_broadcaster phase_broadcas
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ad_ip_instance axis_broadcaster sample_broadcas
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ad_ip_instance axis_broadcaster sample_filtered_broadcas
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ad_ip_instance axis_broadcaster i_q_broadcas
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ad_ip_instance axis_combiner phase_sample_combin
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ad_ip_instance util_axis_resize i_q_resize
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set_property -dict [list \
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CONFIG.MASTER_DATA_WIDTH 32 \
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CONFIG.SLAVE_DATA_WIDTH 64 \
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] $i_q_resize
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ad_ip_parameter i_q_size CONFIG.MASTER_DATA_WIDTH 32
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ad_ip_parameter i_q_size CONFIG.SLAVE_DATA_WIDTH 64
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set hpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 hpf]
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set lpf [create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 lpf]
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ad_ip_instance fir_compiler hpf
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ad_ip_instance fir_compiler lpf
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set_property -dict [list \
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CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
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CONFIG.Data_Sign.VALUE_SRC USER \
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CONFIG.Data_Width.VALUE_SRC USER \
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CONFIG.M_DATA_Has_TREADY true \
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CONFIG.Number_Channels 2 \
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CONFIG.Sample_Frequency 0.025 \
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CONFIG.Clock_Frequency 100 \
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CONFIG.Coefficient_Width 16 \
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CONFIG.Data_Width 24 \
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CONFIG.Output_Width 32 \
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CONFIG.Output_Rounding_Mode Truncate_LSBs \
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CONFIG.Has_ARESETn true \
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CONFIG.Reset_Data_Vector false \
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CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/hpf.mat"] \
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] $hpf
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ad_ip_parameter hpf CONFIG.Data_Fractional_Bits.VALUE_SRC USER
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ad_ip_parameter hpf CONFIG.Data_Sign.VALUE_SRC USER
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ad_ip_parameter hpf CONFIG.Data_Width.VALUE_SRC USER
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ad_ip_parameter hpf CONFIG.M_DATA_Has_TREADY true
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ad_ip_parameter hpf CONFIG.Number_Channels 2
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ad_ip_parameter hpf CONFIG.Sample_Frequency 0.025
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ad_ip_parameter hpf CONFIG.Clock_Frequency 100
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ad_ip_parameter hpf CONFIG.Coefficient_Width 16
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ad_ip_parameter hpf CONFIG.Data_Width 24
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ad_ip_parameter hpf CONFIG.Output_Width 32
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ad_ip_parameter hpf CONFIG.Output_Rounding_Mode Truncate_LSBs
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ad_ip_parameter hpf CONFIG.Has_ARESETn true
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ad_ip_parameter hpf CONFIG.Reset_Data_Vector false
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ad_ip_parameter hpf CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/hpf.mat"]
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set_property -dict [list \
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CONFIG.Data_Fractional_Bits.VALUE_SRC USER \
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CONFIG.Data_Sign.VALUE_SRC USER \
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CONFIG.Data_Width.VALUE_SRC USER \
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CONFIG.M_DATA_Has_TREADY true \
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CONFIG.Number_Channels 4 \
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CONFIG.Sample_Frequency 0.025 \
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CONFIG.Clock_Frequency 100 \
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CONFIG.Coefficient_Width 24 \
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CONFIG.Data_Width 32 \
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CONFIG.Output_Width 32 \
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CONFIG.Output_Rounding_Mode Truncate_LSBs \
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CONFIG.Has_ARESETn true \
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CONFIG.Reset_Data_Vector false \
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CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/lpf.mat"] \
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] $lpf
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ad_ip_parameter lpf CONFIG.Data_Fractional_Bits.VALUE_SRC USER
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ad_ip_parameter lpf CONFIG.Data_Sign.VALUE_SRC USER
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ad_ip_parameter lpf CONFIG.Data_Width.VALUE_SRC USER
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ad_ip_parameter lpf CONFIG.M_DATA_Has_TREADY true
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ad_ip_parameter lpf CONFIG.Number_Channels 4
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ad_ip_parameter lpf CONFIG.Sample_Frequency 0.025
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ad_ip_parameter lpf CONFIG.Clock_Frequency 100
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ad_ip_parameter lpf CONFIG.Coefficient_Width 24
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ad_ip_parameter lpf CONFIG.Data_Width 32
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ad_ip_parameter lpf CONFIG.Output_Width 32
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ad_ip_parameter lpf CONFIG.Output_Rounding_Mode Truncate_LSBs
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ad_ip_parameter lpf CONFIG.Has_ARESETn true
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ad_ip_parameter lpf CONFIG.Reset_Data_Vector false
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ad_ip_parameter lpf CONFIG.CoefficientVector [load_fir_filter_vector "../common/filters/lpf.mat"]
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set overflow_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 overflow_or]
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set_property -dict [list \
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CONFIG.C_SIZE 1 \
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CONFIG.C_OPERATION {or} \
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] $overflow_or
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ad_ip_instance util_vector_logic overflow_or
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ad_ip_parameter overflow_or CONFIG.C_SIZE 1
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ad_ip_parameter overflow_or CONFIG.C_OPERATION or
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ad_connect S_AXIS_SAMPLE phase_data_sync/S_AXIS_SAMPLE
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ad_connect conv_done phase_data_sync/conv_done
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@ -260,10 +246,8 @@ ad_connect /spi/M_AXIS_SAMPLE /processing/S_AXIS_SAMPLE
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ad_connect /spi/conv_done /processing/conv_done
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ad_connect /phase_gen/Q /processing/phase
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set axi_adc [create_bd_cell -type ip -vlnv analog.com:user:axi_generic_adc:1.0 axi_adc]
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set_property -dict [list \
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CONFIG.NUM_OF_CHANNELS 14 \
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] $axi_adc
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ad_ip_instance axi_generic_adc axi_adc
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ad_ip_parameter axi_dac CONFIG.NUM_OF_CHANNELS 14
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ad_connect processing/overflow axi_adc/adc_dovf
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ad_connect axi_adc/adc_enable processing/channel_enable
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@ -2,7 +2,7 @@
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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source ../common/cn0363_bd.tcl
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 35
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set_property LEFT 34 [get_bd_ports GPIO_I]
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set_property LEFT 34 [get_bd_ports GPIO_O]
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