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axi_dmac: Remove unused pause signal from address generator 

The pause signal is not used inside the address generator module. Remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-15 14:26:44 +02:00 committed by István Csomortáni
parent 2b2c1f6a1e
commit 05e8604ea7
4 changed files with 6 additions and 15 deletions
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1
library/axi_dmac/address_generator.v
View File

@ -57,7 +57,6 @@ module dmac_address_generator #(
input eot, input eot,
input enable, input enable,
input pause,
output reg enabled, output reg enabled,
input addr_ready, input addr_ready,

2
library/axi_dmac/dest_axi_mm.v
View File

@ -52,7 +52,6 @@ module dmac_dest_mm_axi #(
input enable, input enable,
output enabled, output enabled,
input pause,
input sync_id, input sync_id,
output sync_id_ret, output sync_id_ret,
@ -139,7 +138,6 @@ dmac_address_generator #(
.enable(enable), .enable(enable),
.enabled(address_enabled), .enabled(address_enabled),
.pause(pause),
.id(address_id), .id(address_id),
.request_id(request_id), .request_id(request_id),

16
library/axi_dmac/request_arb.v
View File

@ -192,12 +192,10 @@ wire sync_id_ret_src;
wire dest_enable; wire dest_enable;
wire dest_enabled; wire dest_enabled;
wire dest_pause;
wire dest_sync_id; wire dest_sync_id;
wire dest_sync_id_ret; wire dest_sync_id_ret;
wire src_enable; wire src_enable;
wire src_enabled; wire src_enabled;
wire src_pause;
wire src_sync_id; wire src_sync_id;
wire src_sync_id_ret; wire src_sync_id_ret;
@ -411,7 +409,6 @@ dmac_dest_mm_axi #(
.enable(dest_enable), .enable(dest_enable),
.enabled(dest_enabled), .enabled(dest_enabled),
.pause(dest_pause),
.req_valid(dest_req_valid), .req_valid(dest_req_valid),
.req_ready(dest_req_ready), .req_ready(dest_req_ready),
@ -623,7 +620,6 @@ dmac_src_mm_axi #(
.m_axi_aclk(m_src_axi_aclk), .m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(src_resetn), .m_axi_aresetn(src_resetn),
.pause(src_pause),
.enable(src_enable), .enable(src_enable),
.enabled(src_enabled), .enabled(src_enabled),
.sync_id(src_sync_id), .sync_id(src_sync_id),
@ -1082,13 +1078,13 @@ dmac_request_generator #(
); );
sync_bits #( sync_bits #(
.NUM_OF_BITS(3), .NUM_OF_BITS(2),
.ASYNC_CLK(ASYNC_CLK_DEST_REQ) .ASYNC_CLK(ASYNC_CLK_DEST_REQ)
) i_sync_control_dest ( ) i_sync_control_dest (
.out_clk(dest_clk), .out_clk(dest_clk),
.out_resetn(dest_resetn), .out_resetn(dest_resetn),
.in({do_enable, pause, sync_id}), .in({do_enable, sync_id}),
.out({dest_enable, dest_pause, dest_sync_id}) .out({dest_enable, dest_sync_id})
); );
sync_bits #( sync_bits #(
@ -1102,13 +1098,13 @@ sync_bits #(
); );
sync_bits #( sync_bits #(
.NUM_OF_BITS(3), .NUM_OF_BITS(2),
.ASYNC_CLK(ASYNC_CLK_REQ_SRC) .ASYNC_CLK(ASYNC_CLK_REQ_SRC)
) i_sync_control_src ( ) i_sync_control_src (
.out_clk(src_clk), .out_clk(src_clk),
.out_resetn(src_resetn), .out_resetn(src_resetn),
.in({do_enable, pause, sync_id}), .in({do_enable, sync_id}),
.out({src_enable, src_pause, src_sync_id}) .out({src_enable, src_sync_id})
); );
sync_bits #( sync_bits #(

2
library/axi_dmac/src_axi_mm.v
View File

@ -52,7 +52,6 @@ module dmac_src_mm_axi #(
input enable, input enable,
output enabled, output enabled,
input pause,
input sync_id, input sync_id,
output sync_id_ret, output sync_id_ret,
@ -131,7 +130,6 @@ dmac_address_generator #(
.enable(enable), .enable(enable),
.enabled(address_enabled), .enabled(address_enabled),
.pause(pause),
.sync_id(sync_id), .sync_id(sync_id),
.request_id(request_id), .request_id(request_id),