jesd204:tb: Update test bench to support dynamic multi-link on TX side

library/jesd204/tb/axi_jesd204_tx_regmap_tb.v

@@ -45,12 +45,13 @@
 module axi_jesd204_tx_tb;
   parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
   parameter NUM_LANES = 2;
+  parameter NUM_LINKS = 2;
 
   `define TIMEOUT 1000000
   `include "tb_base.v"
 
   reg [1:0] core_status_state = 2'b00;
-  reg core_status_sync = 1'b0;
+  reg [NUM_LINKS-1:0] core_status_sync = {NUM_LINKS{1'b0}};
 
   wire s_axi_aclk = clk;
   wire s_axi_aresetn = ~reset;
@@ -239,6 +240,10 @@ module axi_jesd204_tx_tb;
     write_reg_and_update('h200, {NUM_LANES{1'b1}});
     check_all_registers();
 
+    /* Check links disable */
+    write_reg_and_update('h204, {NUM_LANES{1'b1}});
+    check_all_registers();
+
     /* Check JESD common config */
     write_reg_and_update('h210, 32'hff03ff);
     check_all_registers();
@@ -254,23 +259,23 @@ module axi_jesd204_tx_tb;
     check_all_registers();
 
     /* Check status register */
-    core_status_state = 2'b01;
+    core_status_state = 2'b01;  /* CGS */
     set_reset_reg_value('h280, 32'h00000001);
     check_all_registers();
-    core_status_state = 2'b10;
+    core_status_state = 2'b10; /* ILAS */
     set_reset_reg_value('h280, 32'h00000002);
     check_all_registers();
-    core_status_state = 2'b11;
+    core_status_state = 2'b11; /* DATA */
     set_reset_reg_value('h280, 32'h00000003);
     check_all_registers();
-    core_status_state = 2'b00;
+    core_status_state = 2'b00; /* WAIT */
     set_reset_reg_value('h280, 32'h00000000);
     check_all_registers();
 
-    core_status_sync = 1'b1;
+    core_status_sync = {NUM_LINKS{1'b1}}; /* SYNC deasserted */
-    set_reset_reg_value('h280, 32'h00000010);
+    set_reset_reg_value('h280, ({NUM_LINKS{1'b1}} << 4));
     check_all_registers();
-    core_status_sync = 1'b0;
+    core_status_sync = {NUM_LINKS{1'b0}}; /* SYNC asserted */
     set_reset_reg_value('h280, 32'h00000000);
     check_all_registers();
 
@@ -289,6 +294,7 @@ module axi_jesd204_tx_tb;
 
     /* Should be read-only when core is out of reset */
     invert_register('h200);
+    invert_register('h204);
     invert_register('h210);
     invert_register('h214);
     invert_register('h240);
@@ -315,7 +321,8 @@ module axi_jesd204_tx_tb;
   always @(*) #4 core_clk <= ~core_clk;
 
   axi_jesd204_tx #(
-    .NUM_LANES(NUM_LANES)
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS)
   ) i_axi (
     .s_axi_aclk(s_axi_aclk),
     .s_axi_aresetn(s_axi_aresetn),

library/jesd204/tb/loopback_tb.v

@@ -45,6 +45,7 @@
 module loopback_tb;
   parameter VCD_FILE = "loopback_tb.vcd";
   parameter NUM_LANES = 4;
+  parameter NUM_LINKS = 1;
   parameter OCTETS_PER_FRAME = 4;
   parameter FRAMES_PER_MULTIFRAME = 16;
   parameter ENABLE_SCRAMBLER = 1;
@@ -95,7 +96,7 @@ module loopback_tb;
   wire [NUM_LANES*4-1:0] phy_charisk_out;
   wire [NUM_LANES*32-1:0] phy_data_in;
   wire [NUM_LANES*4-1:0] phy_charisk_in;
-  wire sync;
+  wire [NUM_LINKS-1:0] sync;
 
   reg [5:0] sysref_counter = 'h00;
   reg sysref_rx = 1'b0;
@@ -133,6 +134,7 @@ module loopback_tb;
   end endgenerate
 
   wire [NUM_LANES-1:0] tx_cfg_lanes_disable;
+  wire [NUM_LINKS-1:0] tx_cfg_links_disable;
   wire [7:0] tx_cfg_beats_per_multiframe;
   wire [7:0] tx_cfg_octets_per_frame;
   wire [7:0] tx_cfg_lmfc_offset;
@@ -151,6 +153,7 @@ module loopback_tb;
 
   jesd204_tx_static_config #(
     .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS),
     .OCTETS_PER_FRAME(OCTETS_PER_FRAME),
     .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME),
     .SCR(ENABLE_SCRAMBLER)
@@ -158,6 +161,7 @@ module loopback_tb;
     .clk(clk),
 
     .cfg_lanes_disable(tx_cfg_lanes_disable),
+    .cfg_links_disable(tx_cfg_links_disable),
     .cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
     .cfg_octets_per_frame(tx_cfg_octets_per_frame),
     .cfg_lmfc_offset(tx_cfg_lmfc_offset),
@@ -176,12 +180,14 @@ module loopback_tb;
   );
 
   jesd204_tx #(
-    .NUM_LANES(NUM_LANES)
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS)
   ) i_tx (
     .clk(clk),
     .reset(reset),
 
     .cfg_lanes_disable(tx_cfg_lanes_disable),
+    .cfg_links_disable(tx_cfg_links_disable),
     .cfg_beats_per_multiframe(tx_cfg_beats_per_multiframe),
     .cfg_octets_per_frame(tx_cfg_octets_per_frame),
     .cfg_lmfc_offset(tx_cfg_lmfc_offset),

library/jesd204/tb/tx_tb.v

@@ -45,6 +45,7 @@
 module tx_tb;
   parameter VCD_FILE = "tx_tb.vcd";
   parameter NUM_LANES = 1;
+  parameter NUM_LINKS = 1;
   parameter OCTETS_PER_FRAME = 4;
   parameter FRAMES_PER_MULTIFRAME = 32;
 
@@ -61,19 +62,20 @@ module tx_tb;
     end
   end
 
-  reg sync = 1'b1;
+  reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
   reg [31:0] counter = 'h00;
 
   always @(posedge clk) begin
     counter <= counter + 1'b1;
     if (counter >= 'h10 && counter <= 'h30) begin
-      sync <= 1'b0;
+      sync <= {NUM_LINKS{1'b0}};
     end else begin
-      sync <= 1'b1;
+      sync <= {NUM_LINKS{1'b1}};
     end
   end
 
   wire [NUM_LANES-1:0] cfg_lanes_disable;
+  wire [NUM_LINKS-1:0] cfg_links_disable;
   wire [7:0] cfg_beats_per_multiframe;
   wire [7:0] cfg_octets_per_frame;
   wire [7:0] cfg_lmfc_offset;
@@ -92,10 +94,12 @@ module tx_tb;
 
   jesd204_tx_static_config #(
     .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS),
     .OCTETS_PER_FRAME(OCTETS_PER_FRAME),
     .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
   ) i_cfg (
     .cfg_lanes_disable(cfg_lanes_disable),
+    .cfg_links_disable(cfg_links_disable),
     .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
     .cfg_octets_per_frame(cfg_octets_per_frame),
     .cfg_lmfc_offset(cfg_lmfc_offset),
@@ -114,12 +118,14 @@ module tx_tb;
   );
 
   jesd204_tx #(
-    .NUM_LANES(NUM_LANES)
+    .NUM_LANES(NUM_LANES),
+    .NUM_LINKS(NUM_LINKS)
   ) i_tx (
     .clk(clk),
     .reset(reset),
 
     .cfg_lanes_disable(cfg_lanes_disable),
+    .cfg_links_disable(cfg_links_disable),
     .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
     .cfg_octets_per_frame(cfg_octets_per_frame),
     .cfg_lmfc_offset(cfg_lmfc_offset),