daq3/a10gx- qsys modifications
parent
39d23032f1
commit
05ac271aff
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@ -82,15 +82,21 @@ ad_alt_intf signal tx_data output 128 data
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ad_alt_intf clock dac_clk output 1
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add_interface fifo_ch_0_out conduit end
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add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1
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add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1
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add_interface_port fifo_ch_0_out dac_ddata_0 data Input 64
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add_interface dac_ch_0 conduit end
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add_interface_port dac_ch_0 dac_enable_0 enable Output 1
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add_interface_port dac_ch_0 dac_valid_0 valid Output 1
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add_interface_port dac_ch_0 dac_ddata_0 data Input 64
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add_interface fifo_ch_1_out conduit end
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add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1
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add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1
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add_interface_port fifo_ch_1_out dac_ddata_1 data Input 64
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set_interface_property dac_ch_0 associatedClock if_tx_clk
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set_interface_property dac_ch_0 associatedReset none
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add_interface dac_ch_1 conduit end
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add_interface_port dac_ch_1 dac_enable_1 enable Output 1
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add_interface_port dac_ch_1 dac_valid_1 valid Output 1
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add_interface_port dac_ch_1 dac_ddata_1 data Input 64
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set_interface_property dac_ch_1 associatedClock if_tx_clk
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set_interface_property dac_ch_1 associatedReset none
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ad_alt_intf signal dac_dovf input 1 ovf
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ad_alt_intf signal dac_dunf input 1 unf
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