From 05ac271aff9d1bf411974124681270a66ea20ba4 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 24 May 2016 03:15:24 -0400 Subject: [PATCH] daq3/a10gx- qsys modifications --- library/axi_ad9152/axi_ad9152_hw.tcl | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index 27c96ffd0..e2642f384 100755 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -82,15 +82,21 @@ ad_alt_intf signal tx_data output 128 data ad_alt_intf clock dac_clk output 1 -add_interface fifo_ch_0_out conduit end -add_interface_port fifo_ch_0_out dac_enable_0 enable Output 1 -add_interface_port fifo_ch_0_out dac_valid_0 valid Output 1 -add_interface_port fifo_ch_0_out dac_ddata_0 data Input 64 +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_0 valid Output 1 +add_interface_port dac_ch_0 dac_ddata_0 data Input 64 -add_interface fifo_ch_1_out conduit end -add_interface_port fifo_ch_1_out dac_enable_1 enable Output 1 -add_interface_port fifo_ch_1_out dac_valid_1 valid Output 1 -add_interface_port fifo_ch_1_out dac_ddata_1 data Input 64 +set_interface_property dac_ch_0 associatedClock if_tx_clk +set_interface_property dac_ch_0 associatedReset none + +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_1 enable Output 1 +add_interface_port dac_ch_1 dac_valid_1 valid Output 1 +add_interface_port dac_ch_1 dac_ddata_1 data Input 64 + +set_interface_property dac_ch_1 associatedClock if_tx_clk +set_interface_property dac_ch_1 associatedReset none ad_alt_intf signal dac_dovf input 1 ovf ad_alt_intf signal dac_dunf input 1 unf