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AD777x support for ZedBoard and DE10Nano (#937) 

* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.

* library/axi_ad777x: Initial commit for Xilinx and Intel

* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
main
PopPaul2021 2022-08-10 11:29:05 +03:00 committed by GitHub
parent ab29f21f7a
commit 0595f93452
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22 changed files with 1786 additions and 8 deletions
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2
library/Makefile
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@ -16,6 +16,7 @@ clean:
$(MAKE) -C ad463x_data_capture clean
$(MAKE) -C axi_ad5766 clean
$(MAKE) -C axi_ad7616 clean
$(MAKE) -C axi_ad777x clean
$(MAKE) -C axi_ad9122 clean
$(MAKE) -C axi_ad9250 clean
$(MAKE) -C axi_ad9265 clean
@ -135,6 +136,7 @@ lib:
$(MAKE) -C ad463x_data_capture
$(MAKE) -C axi_ad5766
$(MAKE) -C axi_ad7616
$(MAKE) -C axi_ad777x
$(MAKE) -C axi_ad9122
$(MAKE) -C axi_ad9250
$(MAKE) -C axi_ad9265

35
library/axi_ad777x/Makefile Normal file
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####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ad777x
GENERIC_DEPS += ../common/ad_datafmt.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_delay_cntrl.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad777x.v
GENERIC_DEPS += axi_ad777x_if.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad777x_ip.tcl
INTEL_DEPS += ../intel/common/ad_dcfilter.v
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += axi_ad777x_hw.tcl
include ../scripts/library.mk

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library/axi_ad777x/axi_ad777x.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad777x #(
parameter ID = 0
) (
input adc_dovf,
input clk_in,
input ready_in,
output sync_adc_mosi,
input sync_adc_miso,
input [ 3:0] data_in,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_valid_0,
output adc_valid_1,
output adc_valid_2,
output adc_valid_3,
output adc_valid_4,
output adc_valid_5,
output adc_valid_6,
output adc_valid_7,
output [31:0] adc_data_0,
output [31:0] adc_data_1,
output [31:0] adc_data_2,
output [31:0] adc_data_3,
output [31:0] adc_data_4,
output [31:0] adc_data_5,
output [31:0] adc_data_6,
output [31:0] adc_data_7,
output adc_clk,
output adc_reset,
output adc_valid,
output [ 7:0] adc_crc_ch_mismatch,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
// internal signals
wire adc_rst_s;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire adc_clk_s;
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire [7:0] adc_enable;
wire [4:0] adc_num_lanes;
wire adc_crc_enable;
wire [7:0] adc_status_header[0:7];
wire [7:0] adc_crc_err;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk = adc_clk_s;
assign adc_reset = adc_rst_s;
assign adc_enable_0 = adc_enable[0];
assign adc_enable_1 = adc_enable[1];
assign adc_enable_2 = adc_enable[2];
assign adc_enable_3 = adc_enable[3];
assign adc_enable_4 = adc_enable[4];
assign adc_enable_5 = adc_enable[5];
assign adc_enable_6 = adc_enable[6];
assign adc_enable_7 = adc_enable[7];
assign adc_valid_0 = adc_valid;
assign adc_valid_1 = adc_valid;
assign adc_valid_2 = adc_valid;
assign adc_valid_3 = adc_valid;
assign adc_valid_4 = adc_valid;
assign adc_valid_5 = adc_valid;
assign adc_valid_6 = adc_valid;
assign adc_valid_7 = adc_valid;
assign adc_crc_ch_mismatch = adc_crc_err;
integer j;
always @(*) begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= 8; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
end
// adc channels
generate
genvar i;
for (i = 0; i < 8; i=i+1) begin : ad777x_channels
up_adc_channel #(
.CHANNEL_ID(i)
) i_up_adc_channel (
.adc_clk (adc_clk_s),
.adc_rst (adc_rst_s),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (1'b0),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_status_header(adc_status_header[i]),
.adc_crc_err(adc_crc_err[i]),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
end
endgenerate
// adc interface
axi_ad777x_if i_ad777x_if (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
.adc_clk (adc_clk_s),
.adc_valid (adc_valid),
.sync_adc_mosi(sync_adc_mosi),
.sync_adc_miso(sync_adc_miso),
.adc_crc_ch_mismatch(adc_crc_err),
.adc_num_lanes(adc_num_lanes),
.adc_crc_enable(adc_crc_enable),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.adc_status_0(adc_status_header[0]),
.adc_status_1(adc_status_header[1]),
.adc_status_2(adc_status_header[2]),
.adc_status_3(adc_status_header[3]),
.adc_status_4(adc_status_header[4]),
.adc_status_5(adc_status_header[5]),
.adc_status_6(adc_status_header[6]),
.adc_status_7(adc_status_header[7]));
// adc up common
up_adc_common #(
.ID(ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk_s),
.adc_rst (adc_rst_s),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_sync_status (1'b1),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.adc_ext_sync_arm(),
.adc_ext_sync_disarm(),
.adc_ext_sync_manual_req(),
.adc_custom_control(),
.adc_sdr_ddr_n(),
.adc_symb_op(),
.adc_symb_8_16b(),
.adc_num_lanes(adc_num_lanes),
.adc_crc_enable(adc_crc_enable),
.up_pps_rcounter (32'b0),
.up_pps_status (1'b0),
.up_pps_irq_mask (),
.up_adc_ce (),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.up_adc_r1_mode(),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (8),
.up_adc_gpio_in (32'b0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[8]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[8]),
.up_rack (up_rack_s[8]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

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library/axi_ad777x/axi_ad777x_hw.tcl Normal file
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package require qsys
source ../../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad777x
set_module_property DESCRIPTION "AXI AD777x IP"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad777x
# source files
ad_ip_files axi_ad777x [list\
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
$ad_hdl_dir/library/intel/common/ad_dcfilter.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/ad_datafmt.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_delay_cntrl.v \
$ad_hdl_dir/library/common/up_adc_channel.v \
$ad_hdl_dir/library/common/up_adc_common.v \
axi_ad777x_if.v \
axi_ad777x.v ]
# IP parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME "ID"
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
# adc clock interface
add_interface adc_if conduit end
set_interface_property adc_if associatedClock clk_in
add_interface_port adc_if ready_in adc_ready Input 1
add_interface_port adc_if data_in adc_data_in Input 4
add_interface_port adc_if sync_adc_miso sync_adc_miso Input 1
add_interface_port adc_if sync_adc_mosi sync_adc_mosi Output 1
ad_interface signal clk_in input 1
ad_interface clock adc_clk output 1
ad_interface reset adc_reset output 1
set_interface_property if_adc_reset associatedClock if_adc_clk
ad_interface signal adc_crc_ch_mismatch output 8
ad_interface signal adc_dovf input 1 ovf
add_interface adc_ch_0 conduit end
add_interface_port adc_ch_0 adc_enable_0 enable Output 1
add_interface_port adc_ch_0 adc_data_0 data Output 32
add_interface_port adc_ch_0 adc_valid_0 valid Output 1
set_interface_property adc_ch_0 associatedClock if_adc_clk
set_interface_property adc_ch_0 associatedReset none
add_interface adc_ch_1 conduit end
add_interface_port adc_ch_1 adc_enable_1 enable Output 1
add_interface_port adc_ch_1 adc_data_1 data Output 32
add_interface_port adc_ch_1 adc_valid_1 valid Output 1
set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset none
add_interface adc_ch_2 conduit end
add_interface_port adc_ch_2 adc_enable_2 enable Output 1
add_interface_port adc_ch_2 adc_data_2 data Output 32
add_interface_port adc_ch_2 adc_valid_2 valid Output 1
set_interface_property adc_ch_2 associatedClock if_adc_clk
set_interface_property adc_ch_2 associatedReset none
add_interface adc_ch_3 conduit end
add_interface_port adc_ch_3 adc_enable_3 enable Output 1
add_interface_port adc_ch_3 adc_data_3 data Output 32
add_interface_port adc_ch_3 adc_valid_3 valid Output 1
set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
add_interface adc_ch_4 conduit end
add_interface_port adc_ch_4 adc_enable_4 enable Output 1
add_interface_port adc_ch_4 adc_data_4 data Output 32
add_interface_port adc_ch_4 adc_valid_4 valid Output 1
set_interface_property adc_ch_4 associatedClock if_adc_clk
set_interface_property adc_ch_4 associatedReset none
add_interface adc_ch_5 conduit end
add_interface_port adc_ch_5 adc_enable_5 enable Output 1
add_interface_port adc_ch_5 adc_data_5 data Output 32
add_interface_port adc_ch_5 adc_valid_5 valid Output 1
set_interface_property adc_ch_5 associatedClock if_adc_clk
set_interface_property adc_ch_5 associatedReset none
add_interface adc_ch_6 conduit end
add_interface_port adc_ch_6 adc_enable_6 enable Output 1
add_interface_port adc_ch_6 adc_data_6 data Output 32
add_interface_port adc_ch_6 adc_valid_6 valid Output 1
set_interface_property adc_ch_6 associatedClock if_adc_clk
set_interface_property adc_ch_6 associatedReset none
add_interface adc_ch_7 conduit end
add_interface_port adc_ch_7 adc_enable_7 enable Output 1
add_interface_port adc_ch_7 adc_data_7 data Output 32
add_interface_port adc_ch_7 adc_valid_7 valid Output 1
set_interface_property adc_ch_7 associatedClock if_adc_clk
set_interface_property adc_ch_7 associatedReset none

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library/axi_ad777x/axi_ad777x_if.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad777x_if (
// device-interface
input clk_in,
input ready_in,
output sync_adc_mosi,
input sync_adc_miso,
input [ 3:0] data_in,
input [ 4:0] adc_num_lanes,
input adc_crc_enable,
// data path interface
output adc_clk,
output adc_valid,
output [ 7:0] adc_crc_ch_mismatch,
output [31:0] adc_data_0,
output [31:0] adc_data_1,
output [31:0] adc_data_2,
output [31:0] adc_data_3,
output [31:0] adc_data_4,
output [31:0] adc_data_5,
output [31:0] adc_data_6,
output [31:0] adc_data_7,
output [ 7:0] adc_status_0,
output [ 7:0] adc_status_1,
output [ 7:0] adc_status_2,
output [ 7:0] adc_status_3,
output [ 7:0] adc_status_4,
output [ 7:0] adc_status_5,
output [ 7:0] adc_status_6,
output [ 7:0] adc_status_7
);
// internal registers
reg [ 8:0] adc_cnt_p = 'd0;
reg adc_valid_p = 'd0;
reg [255:0] adc_data_p = 'd0;
reg [31:0] adc_data_0_s = 'd0;
reg [31:0] adc_data_1_s = 'd0;
reg [31:0] adc_data_2_s = 'd0;
reg [31:0] adc_data_3_s = 'd0;
reg [31:0] adc_data_4_s = 'd0;
reg [31:0] adc_data_5_s = 'd0;
reg [31:0] adc_data_6_s = 'd0;
reg [31:0] adc_data_7_s = 'd0;
reg [31:0] adc_data_0_s_d = 'd0;
reg [31:0] adc_data_1_s_d = 'd0;
reg [31:0] adc_data_2_s_d = 'd0;
reg [31:0] adc_data_3_s_d = 'd0;
reg [31:0] adc_data_4_s_d = 'd0;
reg [31:0] adc_data_5_s_d = 'd0;
reg [31:0] adc_data_6_s_d = 'd0;
reg [31:0] adc_data_7_s_d = 'd0;
reg adc_valid_s = 'b0;
reg adc_valid_s_d = 'b0;
reg [ 7:0] adc_crc_read_data_0_1 = 'd0;
reg [ 7:0] adc_crc_read_data_2_3 = 'd0;
reg [ 7:0] adc_crc_read_data_4_5 = 'd0;
reg [ 7:0] adc_crc_read_data_6_7 = 'd0;
reg [55:0] adc_crc_data_0_1 = 'd0;
reg [55:0] adc_crc_data_2_3 = 'd0;
reg [55:0] adc_crc_data_4_5 = 'd0;
reg [55:0] adc_crc_data_6_7 = 'd0;
reg [ 7:0] adc_crc_reg_0_1 = 'd0;
reg [ 7:0] adc_crc_reg_2_3 = 'd0;
reg [ 7:0] adc_crc_reg_4_5 = 'd0;
reg [ 7:0] adc_crc_reg_6_7 = 'd0;
reg [ 7:0] adc_status_0_s = 'd0;
reg [ 7:0] adc_status_1_s = 'd0;
reg [ 7:0] adc_status_2_s = 'd0;
reg [ 7:0] adc_status_3_s = 'd0;
reg [ 7:0] adc_status_4_s = 'd0;
reg [ 7:0] adc_status_5_s = 'd0;
reg [ 7:0] adc_status_6_s = 'd0;
reg [ 7:0] adc_status_7_s = 'd0;
reg [ 7:0] adc_crc_ch_mismatch_s = 'd0;
// internal signals
wire adc_cnt_enable_s;
wire adc_ready_in_s;
wire [ 8:0] adc_cnt_value;
wire [ 7:0] adc_crc_in_s_0_1;
wire [ 7:0] adc_crc_in_s_2_3;
wire [ 7:0] adc_crc_in_s_4_5;
wire [ 7:0] adc_crc_in_s_6_7;
wire [ 7:0] adc_crc_s_0_1;
wire [ 7:0] adc_crc_s_2_3;
wire [ 7:0] adc_crc_s_4_5;
wire [ 7:0] adc_crc_s_6_7;
wire adc_crc_mismatch_s_0_1;
wire adc_crc_mismatch_s_2_3;
wire adc_crc_mismatch_s_4_5;
wire adc_crc_mismatch_s_6_7;
assign adc_valid = adc_valid_s_d;
assign adc_ready_in_s = ready_in;
assign adc_data_0 = adc_data_0_s_d;
assign adc_data_1 = adc_data_1_s_d;
assign adc_data_2 = adc_data_2_s_d;
assign adc_data_3 = adc_data_3_s_d;
assign adc_data_4 = adc_data_4_s_d;
assign adc_data_5 = adc_data_5_s_d;
assign adc_data_6 = adc_data_6_s_d;
assign adc_data_7 = adc_data_7_s_d;
assign sync_adc_mosi = sync_adc_miso;
assign adc_clk = clk_in;
assign adc_status_0 = adc_status_0_s;
assign adc_status_1 = adc_status_1_s;
assign adc_status_2 = adc_status_2_s;
assign adc_status_3 = adc_status_3_s;
assign adc_status_4 = adc_status_4_s;
assign adc_status_5 = adc_status_5_s;
assign adc_status_6 = adc_status_6_s;
assign adc_status_7 = adc_status_7_s;
assign adc_crc_ch_mismatch = adc_crc_ch_mismatch_s;
// function (crc)
function [ 7:0] crc8;
input [55:0] din;
input [ 7:0] cin;
reg [ 7:0] cout;
begin
cout[0] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 8] ^ din[12] ^ din[14] ^ din[16] ^
din[18] ^ din[19] ^ din[21] ^ din[23] ^ din[28] ^ din[30] ^ din[31] ^ din[34] ^ din[35] ^ din[39] ^ din[40] ^ din[43] ^ din[45] ^
din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[53] ^ din[54];
cout[1] = cin[ 0] ^ cin[ 3] ^ cin[ 4] ^ cin[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23] ^ din[24] ^ din[28] ^ din[29] ^ din[30] ^ din[32] ^ din[34] ^ din[36] ^
din[39] ^ din[41] ^ din[43] ^ din[44] ^ din[45] ^ din[46] ^ din[48] ^ din[51] ^ din[52] ^ din[55];
cout[2] = cin[ 0] ^ cin[ 2] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^ din[12] ^ din[13] ^ din[15] ^ din[17] ^
din[22] ^ din[24] ^ din[25] ^ din[28] ^ din[29] ^ din[33] ^ din[34] ^ din[37] ^ din[39] ^ din[42] ^ din[43] ^ din[44] ^ din[46] ^
din[47] ^ din[48] ^ din[50] ^ din[54];
cout[3] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^ din[11] ^ din[13] ^ din[14] ^ din[16] ^
din[18] ^ din[23] ^ din[25] ^ din[26] ^ din[29] ^ din[30] ^ din[34] ^ din[35] ^ din[38] ^ din[40] ^ din[43] ^ din[44] ^ din[45] ^
din[47] ^ din[48] ^ din[49] ^ din[51] ^ din[55];
cout[4] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^ din[14] ^ din[15] ^ din[17] ^
din[19] ^ din[24] ^ din[26] ^ din[27] ^ din[30] ^ din[31] ^ din[35] ^ din[36] ^ din[39] ^ din[41] ^ din[44] ^ din[45] ^ din[46] ^
din[48] ^ din[49] ^ din[50] ^ din[52];
cout[5] = cin[ 1] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^ din[13] ^ din[15] ^ din[16] ^ din[18] ^
din[20] ^ din[25] ^ din[27] ^ din[28] ^ din[31] ^ din[32] ^ din[36] ^ din[37] ^ din[40] ^ din[42] ^ din[45] ^ din[46] ^ din[47] ^
din[49] ^ din[50] ^ din[51] ^ din[53];
cout[6] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 4] ^ cin[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^ din[12] ^ din[14] ^ din[16] ^ din[17] ^
din[19] ^ din[21] ^ din[26] ^ din[28] ^ din[29] ^ din[32] ^ din[33] ^ din[37] ^ din[38] ^ din[41] ^ din[43] ^ din[46] ^ din[47] ^
din[48] ^ din[50] ^ din[51] ^ din[52] ^ din[54];
cout[7] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 4] ^ cin[ 5] ^ cin[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^
din[18] ^ din[20] ^ din[22] ^ din[27] ^ din[29] ^ din[30] ^ din[33] ^ din[34] ^ din[38] ^ din[39] ^ din[42] ^ din[44] ^ din[47] ^
din[48] ^ din[49] ^ din[51] ^ din[52] ^ din[53] ^ din[55];
crc8 = cout;
end
endfunction
//crc computing
assign adc_crc_s_0_1 = crc8(adc_crc_data_0_1, adc_crc_in_s_0_1);
assign adc_crc_s_2_3 = crc8(adc_crc_data_2_3, adc_crc_in_s_2_3);
assign adc_crc_s_4_5 = crc8(adc_crc_data_4_5, adc_crc_in_s_4_5);
assign adc_crc_s_6_7 = crc8(adc_crc_data_6_7, adc_crc_in_s_6_7);
assign adc_crc_in_s_0_1 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_0_1;
assign adc_crc_in_s_2_3 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_2_3;
assign adc_crc_in_s_4_5 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_4_5;
assign adc_crc_in_s_6_7 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_6_7;
assign adc_crc_mismatch_s_0_1 = (adc_crc_read_data_0_1 == adc_crc_s_0_1) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s_2_3 = (adc_crc_read_data_2_3 == adc_crc_s_2_3) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s_4_5 = (adc_crc_read_data_4_5 == adc_crc_s_4_5) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s_6_7 = (adc_crc_read_data_6_7 == adc_crc_s_6_7) ? 1'b0 : adc_crc_enable;
always @(posedge adc_clk) begin
adc_status_0_s <= (adc_valid_s == 1'b1 ) ? adc_data_0_s[31:24]: adc_status_0_s;
adc_status_1_s <= (adc_valid_s == 1'b1 ) ? adc_data_1_s[31:24]: adc_status_1_s;
adc_status_2_s <= (adc_valid_s == 1'b1 ) ? adc_data_2_s[31:24]: adc_status_2_s;
adc_status_3_s <= (adc_valid_s == 1'b1 ) ? adc_data_3_s[31:24]: adc_status_3_s;
adc_status_4_s <= (adc_valid_s == 1'b1 ) ? adc_data_4_s[31:24]: adc_status_4_s;
adc_status_5_s <= (adc_valid_s == 1'b1 ) ? adc_data_5_s[31:24]: adc_status_5_s;
adc_status_6_s <= (adc_valid_s == 1'b1 ) ? adc_data_6_s[31:24]: adc_status_6_s;
adc_status_7_s <= (adc_valid_s == 1'b1 ) ? adc_data_7_s[31:24]: adc_status_7_s;
adc_crc_ch_mismatch_s[1:0] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_0_1}} : adc_crc_ch_mismatch_s[1:0];
adc_crc_ch_mismatch_s[3:2] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_2_3}} : adc_crc_ch_mismatch_s[3:2];
adc_crc_ch_mismatch_s[5:4] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_4_5}} : adc_crc_ch_mismatch_s[5:4];
adc_crc_ch_mismatch_s[7:6] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_6_7}} : adc_crc_ch_mismatch_s[7:6];
end
// crc generation/validation data
always @(posedge adc_clk) begin
if (adc_valid_s == 1'b1) begin
adc_crc_reg_0_1 <= adc_crc_s_0_1;
adc_crc_reg_2_3 <= adc_crc_s_2_3;
adc_crc_reg_4_5 <= adc_crc_s_4_5;
adc_crc_reg_6_7 <= adc_crc_s_6_7;
adc_crc_read_data_0_1 <= {adc_data_0_s[27:24],adc_data_1_s[27:24]};
adc_crc_read_data_2_3 <= {adc_data_2_s[27:24],adc_data_3_s[27:24]};
adc_crc_read_data_4_5 <= {adc_data_4_s[27:24],adc_data_5_s[27:24]};
adc_crc_read_data_6_7 <= {adc_data_6_s[27:24],adc_data_7_s[27:24]};
adc_crc_data_0_1 <= {adc_data_0_s[31:28],adc_data_0_s[23:0],adc_data_1_s[31:28],adc_data_1_s[23:0]};
adc_crc_data_2_3 <= {adc_data_2_s[31:28],adc_data_2_s[23:0],adc_data_3_s[31:28],adc_data_3_s[23:0]};
adc_crc_data_4_5 <= {adc_data_4_s[31:28],adc_data_4_s[23:0],adc_data_5_s[31:28],adc_data_5_s[23:0]};
adc_crc_data_6_7 <= {adc_data_6_s[31:28],adc_data_6_s[23:0],adc_data_7_s[31:28],adc_data_7_s[23:0]};
end else begin
adc_crc_reg_0_1 <= 'd0;
adc_crc_reg_2_3 <= 'd0;
adc_crc_reg_4_5 <= 'd0;
adc_crc_reg_6_7 <= 'd0;
adc_crc_read_data_0_1 <= 'd0;
adc_crc_read_data_2_3 <= 'd0;
adc_crc_read_data_4_5 <= 'd0;
adc_crc_read_data_6_7 <= 'd0;
adc_crc_data_0_1 <= 'd0;
adc_crc_data_2_3 <= 'd0;
adc_crc_data_4_5 <= 'd0;
adc_crc_data_6_7 <= 'd0;
end
end
//delay data 1 clk for data, data_valid and crc mismatch for alignment
always @(posedge adc_clk) begin
if (adc_valid_s == 1'b1) begin
adc_data_0_s_d <= adc_data_0_s;
adc_data_1_s_d <= adc_data_1_s;
adc_data_2_s_d <= adc_data_2_s;
adc_data_3_s_d <= adc_data_3_s;
adc_data_4_s_d <= adc_data_4_s;
adc_data_5_s_d <= adc_data_5_s;
adc_data_6_s_d <= adc_data_6_s;
adc_data_7_s_d <= adc_data_7_s;
adc_valid_s_d <= adc_valid_s;
end else begin
adc_data_0_s_d <= 32'b0;
adc_data_1_s_d <= 32'b0;
adc_data_2_s_d <= 32'b0;
adc_data_3_s_d <= 32'b0;
adc_data_4_s_d <= 32'b0;
adc_data_5_s_d <= 32'b0;
adc_data_6_s_d <= 32'b0;
adc_data_7_s_d <= 32'b0;
adc_valid_s_d <= 1'b0;
end
end
always @(posedge adc_clk) begin
if (adc_valid_p == 1'b1) begin
if( adc_num_lanes == 'h1) begin
adc_data_0_s <= adc_data_p[((32*7)+31):(32*7)];
adc_data_1_s <= adc_data_p[((32*6)+31):(32*6)];
adc_data_2_s <= adc_data_p[((32*5)+31):(32*5)];
adc_data_3_s <= adc_data_p[((32*4)+31):(32*4)];
adc_data_4_s <= adc_data_p[((32*3)+31):(32*3)];
adc_data_5_s <= adc_data_p[((32*2)+31):(32*2)];
adc_data_6_s <= adc_data_p[((32*1)+31):(32*1)];
adc_data_7_s <= adc_data_p[((32*0)+31):(32*0)];
end else if( adc_num_lanes == 'h2) begin
adc_data_0_s <= adc_data_p[((32*3)+31):(32*3)];
adc_data_1_s <= adc_data_p[((32*2)+31):(32*2)];
adc_data_2_s <= adc_data_p[((32*1)+31):(32*1)];
adc_data_3_s <= adc_data_p[((32*0)+31):(32*0)];
adc_data_4_s <= adc_data_p[((32*7)+31):(32*7)];
adc_data_5_s <= adc_data_p[((32*6)+31):(32*6)];
adc_data_6_s <= adc_data_p[((32*5)+31):(32*5)];
adc_data_7_s <= adc_data_p[((32*4)+31):(32*4)];
end else begin
adc_data_0_s <= adc_data_p[((32*1)+31):(32*1)];
adc_data_1_s <= adc_data_p[((32*0)+31):(32*0)];
adc_data_2_s <= adc_data_p[((32*3)+31):(32*3)];
adc_data_3_s <= adc_data_p[((32*2)+31):(32*2)];
adc_data_4_s <= adc_data_p[((32*5)+31):(32*5)];
adc_data_5_s <= adc_data_p[((32*4)+31):(32*4)];
adc_data_6_s <= adc_data_p[((32*7)+31):(32*7)];
adc_data_7_s <= adc_data_p[((32*6)+31):(32*6)];
end
adc_valid_s <= adc_valid_p;
end else begin
adc_data_0_s <= 32'b0;
adc_data_1_s <= 32'b0;
adc_data_2_s <= 32'b0;
adc_data_3_s <= 32'b0;
adc_data_4_s <= 32'b0;
adc_data_5_s <= 32'b0;
adc_data_6_s <= 32'b0;
adc_data_7_s <= 32'b0;
adc_valid_s <= 1'b0;
end
end
assign adc_cnt_value = (adc_num_lanes == 'h1) ? 'hff :
((adc_num_lanes == 'h2)? 'h7f : 'h3f);
assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0;
always @(negedge adc_clk) begin
if (adc_ready_in_s == 1'b1) begin
adc_cnt_p <= 'h000;
end else if (adc_cnt_enable_s == 1'b1) begin
adc_cnt_p <= adc_cnt_p + 1'b1;
end
if (adc_cnt_p == adc_cnt_value) begin
adc_valid_p <= 1'b1;
end else begin
adc_valid_p <= 1'b0;
end
end
// data (individual lanes)
always @(negedge adc_clk) begin
if( adc_num_lanes == 'h1) begin
if (adc_cnt_p == 'h000 ) begin
adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]};
end else begin
adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]};
end
end else if( adc_num_lanes == 'h2) begin
if (adc_cnt_p == 'h000 ) begin
adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]};
end else begin
adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]};
end
end else begin
if (adc_cnt_p == 'h000 ) begin
adc_data_p[((64*0)+63):(64*0)] <= {63'd0, data_in[0]};
adc_data_p[((64*1)+63):(64*1)] <= {63'd0, data_in[1]};
adc_data_p[((64*2)+63):(64*2)] <= {63'd0, data_in[2]};
adc_data_p[((64*3)+63):(64*3)] <= {63'd0, data_in[3]};
end else begin
adc_data_p[((64*0)+63):(64*0)] <= {adc_data_p[((64*0)+62):(64*0)], data_in[0]};
adc_data_p[((64*1)+63):(64*1)] <= {adc_data_p[((64*1)+62):(64*1)], data_in[1]};
adc_data_p[((64*2)+63):(64*2)] <= {adc_data_p[((64*2)+62):(64*2)], data_in[2]};
adc_data_p[((64*3)+63):(64*3)] <= {adc_data_p[((64*3)+62):(64*3)], data_in[3]};
end
end
end
endmodule

45
library/axi_ad777x/axi_ad777x_ip.tcl Normal file
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@ -0,0 +1,45 @@
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ad777x
adi_ip_files axi_ad777x [list \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"axi_ad777x_if.v" \
"axi_ad777x.v" ]
adi_ip_properties axi_ad777x
adi_init_bd_tcl
adi_ip_bd axi_ad777x "bd/bd.tcl"
set_property company_url {https://wiki.analog.com/resources/fpga/docs/ad777x} [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface clk_in xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
set_property value "ACTIVE_HIGH" $reset_polarity
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]

18
library/common/up_adc_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -66,6 +66,8 @@ module up_adc_channel #(
input adc_pn_err,
input adc_pn_oos,
input adc_or,
input [ 7:0] adc_status_header,
input adc_crc_err,
output up_adc_pn_err,
output up_adc_pn_oos,
output up_adc_or,
@ -143,6 +145,8 @@ module up_adc_channel #(
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [ 7:0] up_adc_status_header_s;
wire up_adc_crc_err_s;
// 2's complement function
@ -394,7 +398,7 @@ module up_adc_channel #(
up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata_int <= { 29'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int};
4'h1: up_rdata_int <= { 19'd0, up_adc_crc_err_s, up_adc_status_header_s, 1'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int};
4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
4'h6: up_rdata_int <= { 12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
@ -478,16 +482,20 @@ module up_adc_channel #(
adc_data_sel}));
up_xfer_status #(
.DATA_WIDTH(3)
.DATA_WIDTH(12)
) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_adc_pn_err_s,
.up_data_status ({up_adc_status_header_s,
up_adc_crc_err_s,
up_adc_pn_err_s,
up_adc_pn_oos_s,
up_adc_or_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_pn_err,
.d_data_status ({ adc_status_header,
adc_crc_err,
adc_pn_err,
adc_pn_oos,
adc_or}));

12
library/common/up_adc_common.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -75,6 +75,7 @@ module up_adc_common #(
output adc_ext_sync_manual_req,
output [4:0] adc_num_lanes,
output [7:0] adc_custom_control,
output adc_crc_enable,
output adc_sdr_ddr_n,
output adc_symb_op,
output adc_symb_8_16b,
@ -154,6 +155,7 @@ module up_adc_common #(
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
reg [ 7:0] up_adc_custom_control = 'd0;
reg up_adc_crc_enable = 'd0;
// internal signals
@ -205,6 +207,7 @@ module up_adc_common #(
up_adc_pin_mode <= 'd0;
up_pps_irq_mask <= 1'b1;
up_adc_custom_control <= 'd0;
up_adc_crc_enable <= 'd0;
end else begin
up_adc_clk_enb_int <= ~up_adc_clk_enb;
up_core_preset <= ~up_resetn;
@ -249,6 +252,7 @@ module up_adc_common #(
end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin
up_adc_ext_sync_manual_req <= up_wdata[8];
end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h13)) begin
up_adc_crc_enable <= up_wdata[8];
up_adc_custom_control <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin
@ -444,7 +448,7 @@ module up_adc_common #(
3'b0, up_adc_ext_sync_manual_req,
4'b0,
1'b0, up_adc_ext_sync_disarm, up_adc_ext_sync_arm, 1'b0};
7'h13: up_rdata_int <= {24'd0, up_adc_custom_control};
7'h13: up_rdata_int <= {23'd0, up_adc_crc_enable, up_adc_custom_control};
7'h15: up_rdata_int <= up_adc_clk_count_s;
7'h16: up_rdata_int <= adc_clk_ratio;
7'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
@ -487,7 +491,7 @@ module up_adc_common #(
// adc control & status
up_xfer_cntrl #(
.DATA_WIDTH(57)
.DATA_WIDTH(58)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
@ -496,6 +500,7 @@ module up_adc_common #(
up_adc_symb_8_16b,
up_adc_num_lanes,
up_adc_custom_control,
up_adc_crc_enable,
up_adc_sref_sync,
up_adc_ext_sync_arm,
up_adc_ext_sync_disarm,
@ -514,6 +519,7 @@ module up_adc_common #(
adc_symb_8_16b,
adc_num_lanes,
adc_custom_control,
adc_crc_enable,
adc_sref_sync,
adc_ext_sync_arm,
adc_ext_sync_disarm,

7
projects/ad777x_ardz/Makefile Normal file
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@ -0,0 +1,7 @@
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
include ../scripts/project-toplevel.mk

8
projects/ad777x_ardz/Readme.md Normal file
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@ -0,0 +1,8 @@
# AD777x-ARDZ HDL Project
Here are some pointers to help you:
* [Board Product Page](https://www.analog.com/en/products/ad777x.html)
* Parts : [8 Channels, 24-bit simultaneous sampling ADC](https://www.analog.com/en/products/ad777x.html)
* Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad777x-ardz
* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad777x-ardz
* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl

67
projects/ad777x_ardz/common/ad777x_ardz_bd.tcl Normal file
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# ad777x interface
create_bd_port -dir I adc_clk_in
create_bd_port -dir O sync_adc_mosi
create_bd_port -dir I sync_adc_miso
create_bd_port -dir I adc_ready
create_bd_port -dir I -from 3 -to 0 adc_data_in
# adc(ad777x-dma)
ad_ip_instance axi_dmac ad777x_dma
ad_ip_parameter ad777x_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter ad777x_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter ad777x_dma CONFIG.CYCLIC 0
ad_ip_parameter ad777x_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter ad777x_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter ad777x_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter ad777x_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter ad777x_dma CONFIG.DMA_DATA_WIDTH_SRC 256
ad_ip_parameter ad777x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect sys_cpu_resetn ad777x_dma/m_dest_axi_aresetn
# ps7-hp1
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1
# axi_ad777x
ad_ip_instance axi_ad777x axi_ad777x_adc
ad_connect adc_data_in axi_ad777x_adc/data_in
ad_connect adc_clk_in axi_ad777x_adc/clk_in
ad_connect adc_ready axi_ad777x_adc/ready_in
ad_connect sync_adc_mosi axi_ad777x_adc/sync_adc_mosi
ad_connect sync_adc_miso axi_ad777x_adc/sync_adc_miso
ad_connect axi_ad777x_adc/adc_clk ad777x_dma/fifo_wr_clk
# adc-path channel pack
ad_ip_instance util_cpack2 ad777x_adc_pack
ad_ip_parameter ad777x_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter ad777x_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
ad_connect axi_ad777x_adc/adc_clk ad777x_adc_pack/clk
ad_connect axi_ad777x_adc/adc_reset ad777x_adc_pack/reset
ad_connect axi_ad777x_adc/adc_valid ad777x_adc_pack/fifo_wr_en
ad_connect ad777x_adc_pack/packed_fifo_wr ad777x_dma/fifo_wr
ad_connect ad777x_adc_pack/fifo_wr_overflow axi_ad777x_adc/adc_dovf
for {set i 0} {$i < 8} {incr i} {
ad_connect axi_ad777x_adc/adc_data_$i ad777x_adc_pack/fifo_wr_data_$i
ad_connect axi_ad777x_adc/adc_enable_$i ad777x_adc_pack/enable_$i
}
# interrupts
ad_cpu_interrupt ps-10 mb-10 ad777x_dma/irq
# cpu / memory interconnects
ad_cpu_interconnect 0x43c00000 axi_ad777x_adc
ad_cpu_interconnect 0x7c480000 ad777x_dma
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk ad777x_dma/m_dest_axi

71
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# ad777x
add_instance axi_ad777x_adc axi_ad777x
add_interface axi_ad777x_adc_if conduit end
set_interface_property axi_ad777x_adc_if EXPORT_OF axi_ad777x_adc.adc_if
add_interface axi_ad777x_adc_clk_if conduit end
set_interface_property axi_ad777x_adc_clk_if EXPORT_OF axi_ad777x_adc.if_clk_in
# adc-path channel pack
add_instance ad777x_adc_pack util_cpack2
set_instance_parameter_value ad777x_adc_pack {NUM_OF_CHANNELS} {8}
set_instance_parameter_value ad777x_adc_pack {SAMPLE_DATA_WIDTH} {32}
add_connection axi_ad777x_adc.if_adc_clk ad777x_adc_pack.clk
add_connection axi_ad777x_adc.if_adc_reset ad777x_adc_pack.reset
add_connection axi_ad777x_adc.if_adc_dovf ad777x_adc_pack.if_fifo_wr_overflow
add_connection ad777x_adc_pack.adc_ch_0 axi_ad777x_adc.adc_ch_0
add_connection ad777x_adc_pack.adc_ch_1 axi_ad777x_adc.adc_ch_1
add_connection ad777x_adc_pack.adc_ch_2 axi_ad777x_adc.adc_ch_2
add_connection ad777x_adc_pack.adc_ch_3 axi_ad777x_adc.adc_ch_3
add_connection ad777x_adc_pack.adc_ch_4 axi_ad777x_adc.adc_ch_4
add_connection ad777x_adc_pack.adc_ch_5 axi_ad777x_adc.adc_ch_5
add_connection ad777x_adc_pack.adc_ch_6 axi_ad777x_adc.adc_ch_6
add_connection ad777x_adc_pack.adc_ch_7 axi_ad777x_adc.adc_ch_7
# adc(ad777x-dma)
add_instance ad777x_dma axi_dmac
set_instance_parameter_value ad777x_dma {ID} {0}
set_instance_parameter_value ad777x_dma {DMA_DATA_WIDTH_SRC} {256}
set_instance_parameter_value ad777x_dma {DMA_DATA_WIDTH_DEST} {64}
set_instance_parameter_value ad777x_dma {DMA_2D_TRANSFER} {0}
set_instance_parameter_value ad777x_dma {AXI_SLICE_DEST} {0}
set_instance_parameter_value ad777x_dma {AXI_SLICE_SRC} {0}
set_instance_parameter_value ad777x_dma {SYNC_TRANSFER_START} {1}
set_instance_parameter_value ad777x_dma {CYCLIC} {0}
set_instance_parameter_value ad777x_dma {DMA_TYPE_DEST} {0}
set_instance_parameter_value ad777x_dma {DMA_TYPE_SRC} {2}
add_connection sys_clk.clk ad777x_dma.s_axi_clock
add_connection sys_clk.clk ad777x_dma.m_dest_axi_clock
add_connection sys_clk.clk axi_ad777x_adc.s_axi_clock
add_connection axi_ad777x_adc.if_adc_clk ad777x_dma.if_fifo_wr_clk
add_connection ad777x_adc_pack.if_packed_fifo_wr_en ad777x_dma.if_fifo_wr_en
add_connection ad777x_adc_pack.if_packed_fifo_wr_sync ad777x_dma.if_fifo_wr_sync
add_connection ad777x_adc_pack.if_packed_fifo_wr_data ad777x_dma.if_fifo_wr_din
add_connection ad777x_adc_pack.if_packed_fifo_wr_overflow ad777x_dma.if_fifo_wr_overflow
#resets
add_connection sys_dma_clk.clk_reset axi_ad777x_adc.s_axi_reset
add_connection sys_clk.clk_reset ad777x_dma.s_axi_reset
add_connection sys_dma_clk.clk_reset ad777x_dma.m_dest_axi_reset
# interrupts
ad_cpu_interrupt 5 ad777x_dma.interrupt_sender
# cpu interconnects
ad_cpu_interconnect 0x00020000 axi_ad777x_adc.s_axi
ad_cpu_interconnect 0x00030000 ad777x_dma.s_axi
# mem interconnects
ad_dma_interconnect ad777x_dma.m_dest_axi

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@ -0,0 +1,21 @@
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad777x_ardz_de10nano
M_DEPS += ../common/ad777x_ardz_qsys.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
LIB_DEPS += axi_ad777x
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += util_pack/util_cpack2
include ../../scripts/project-intel.mk

15
projects/ad777x_ardz/de10nano/system_constr.sdc Normal file
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@ -0,0 +1,15 @@
create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}]
create_clock -period "488.00 ns" -name adc_clk [get_ports {adc_clk_in}]
derive_pll_clocks
derive_clock_uncertainty
set fall_min 224; # period/2(=244) - skew_bfe(=20)
set fall_max 264; # period/2(=244) + skew_are(=20)
set_input_delay -clock adc_clk -max $fall_max [get_ports adc_data_in[*]] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports adc_data_in[*]] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports adc_ready_in ] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports adc_ready_in ] -clock_fall -add_delay;

48
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set REQUIRED_QUARTUS_VERSION 20.1.1
set QUARTUS_PRO_ISUSED 0
source ../../../scripts/adi_env.tcl
source ../../scripts/adi_project_intel.tcl
adi_project ad777x_ardz_de10nano
source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
# ad777x interface
set_location_assignment PIN_AE15 -to adc_clk_in ; ## P4.2 Arduino_IO09
set_location_assignment PIN_AF17 -to adc_ready_in ; ## P4.1 Arduino_IO08
set_location_assignment PIN_AG8 -to adc_data_in[0] ; ## P5.7 Arduino_IO06
set_location_assignment PIN_U13 -to adc_data_in[1] ; ## P5.6 Arduino_IO05
set_location_assignment PIN_U14 -to adc_data_in[2] ; ## P5.5 Arduino_IO04
set_location_assignment PIN_AG13 -to adc_data_in[3] ; ## P5.1 Arduino_IO00
set_location_assignment PIN_AF13 -to sdp_convst ; ## P5.2 Arduino_IO01
set_location_assignment PIN_AH8 -to start_n ; ## P5.8 Arduino_IO07
set_location_assignment PIN_AG10 -to reset_n ; ## P5.3 Arduino_IO02
set_location_assignment PIN_AG9 -to sdp_mclk ; ## P5.4 Arduino_IO03
set_location_assignment PIN_AF15 -to spi_csn ; ## P4.3 Arduino_IO10
set_location_assignment PIN_AG16 -to spi_mosi ; ## P4.4 Arduino_IO11
set_location_assignment PIN_AH11 -to spi_miso ; ## P4.5 Arduino_IO12
set_location_assignment PIN_AH12 -to spi_clk ; ## P4.5 Arduino_IO13
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_clk_in
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_ready_in
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adc_data_in[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdp_convst
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to start_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to reset_n
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdp_convst
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdp_mclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_csn
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_mosi
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_miso
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spi_clk
execute_flow -compile

13
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
source ../common/ad777x_ardz_qsys.tcl
set_instance_parameter_value sys_spi {clockPolarity} {0}
#system ID
set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
sysid_gen_sys_init_file;

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// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
// hps-ddr
output [14:0] ddr3_a,
output [ 2:0] ddr3_ba,
output ddr3_reset_n,
output ddr3_ck_p,
output ddr3_ck_n,
output ddr3_cke,
output ddr3_cs_n,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
inout [31:0] ddr3_dq,
inout [ 3:0] ddr3_dqs_p,
inout [ 3:0] ddr3_dqs_n,
output [ 3:0] ddr3_dm,
output ddr3_odt,
input ddr3_rzq,
// hps-ethernet
output eth1_tx_clk,
output eth1_tx_ctl,
output [ 3:0] eth1_tx_d,
input eth1_rx_clk,
input eth1_rx_ctl,
input [ 3:0] eth1_rx_d,
output eth1_mdc,
inout eth1_mdio,
// hps-sdio
output sdio_clk,
inout sdio_cmd,
inout [ 3:0] sdio_d,
// hps-spim1
output spim1_ss0,
output spim1_clk,
output spim1_mosi,
input spim1_miso,
// hps-usb
input usb1_clk,
output usb1_stp,
input usb1_dir,
input usb1_nxt,
inout [ 7:0] usb1_d,
// hps-uart
input uart0_rx,
output uart0_tx,
inout hps_conv_usb_n,
// board gpio
output [ 7:0] gpio_bd_o,
input [ 5:0] gpio_bd_i,
// hdmi
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [ 23:0] hdmi_data,
inout hdmi_i2c_scl,
inout hdmi_i2c_sda,
// ad777x
input adc_clk_in,
input adc_ready_in,
input [ 3:0] adc_data_in,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso,
output start_n,
output sdp_convst,
output sdp_mclk,
output reset_n
);
// internal signals
wire sys_resetn;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire i2c1_scl;
wire i2c1_scl_oe;
wire i2c1_sda;
wire i2c1_sda_oe;
wire i2c0_out_data;
wire i2c0_sda;
wire i2c0_out_clk;
wire i2c0_scl_in_clk;
// adc control gpio assign
assign start_n = gpio_o[33];
assign sdp_convst = gpio_o[34];
assign sdp_mclk = gpio_o[35];
assign reset_n = gpio_o[39];
assign gpio_i[63:39] = gpio_o[63:39];
assign gpio_i[35:33] = gpio_o[35:33];
assign gpio_i[31:15] = gpio_o[31:15];
// bd gpio
assign gpio_i[13:8] = gpio_bd_i[5:0];
assign gpio_bd_o[7:0] = gpio_o[7:0];
// IO Buffers for I2C
ALT_IOBUF scl_video_iobuf (
.i(1'b0),
.oe(i2c0_out_clk),
.o(i2c0_scl_in_clk),
.io(hdmi_i2c_scl));
ALT_IOBUF sda_video_iobuf (
.i(1'b0),
.oe(i2c0_out_data),
.o(i2c0_sda),
.io(hdmi_i2c_sda));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_hps_h2f_reset_reset_n (sys_resetn),
.sys_hps_memory_mem_a (ddr3_a),
.sys_hps_memory_mem_ba (ddr3_ba),
.sys_hps_memory_mem_ck (ddr3_ck_p),
.sys_hps_memory_mem_ck_n (ddr3_ck_n),
.sys_hps_memory_mem_cke (ddr3_cke),
.sys_hps_memory_mem_cs_n (ddr3_cs_n),
.sys_hps_memory_mem_ras_n (ddr3_ras_n),
.sys_hps_memory_mem_cas_n (ddr3_cas_n),
.sys_hps_memory_mem_we_n (ddr3_we_n),
.sys_hps_memory_mem_reset_n (ddr3_reset_n),
.sys_hps_memory_mem_dq (ddr3_dq),
.sys_hps_memory_mem_dqs (ddr3_dqs_p),
.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
.sys_hps_memory_mem_odt (ddr3_odt),
.sys_hps_memory_mem_dm (ddr3_dm),
.sys_hps_memory_oct_rzqin (ddr3_rzq),
.sys_rst_reset_n (sys_resetn),
.sys_hps_i2c0_out_data (i2c0_out_data),
.sys_hps_i2c0_sda (i2c0_sda),
.sys_hps_i2c0_clk_clk (i2c0_out_clk),
.sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk),
.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
.sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n),
.sys_hps_i2c1_sda (i2c1_sda),
.sys_hps_i2c1_out_data (i2c1_sda_oe),
.sys_hps_i2c1_clk_clk (i2c1_scl_oe),
.sys_hps_i2c1_scl_in_clk (i2c1_scl),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.axi_ad777x_adc_clk_if_clk_in(adc_clk_in),
.axi_ad777x_adc_if_adc_ready(adc_ready_in),
.axi_ad777x_adc_if_adc_data_in(adc_data_in),
.axi_ad777x_adc_if_sync_adc_mosi(),
.axi_ad777x_adc_if_sync_adc_miso(),
.axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
.axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync),
.axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync),
.axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e),
.axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data));
endmodule

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####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad777x_ardz_zed
M_DEPS += ../common/ad777x_ardz_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
LIB_DEPS += axi_ad777x
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += util_i2c_mixer
LIB_DEPS += util_pack/util_cpack2
include ../../scripts/project-xilinx.mk

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/ad777x_ardz_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file

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set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports adc_clk_in] ; #DCLK P24_P9 JA1_9
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS33} [get_ports adc_ready_in] ; #DRDY_N P24_P8 JA1_8
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports adc_data_in[0]] ; #DOUT0 P24_P10 JA1_10
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports adc_data_in[1]] ; #DOUT1 P30_P2 JC1_1_N
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports adc_data_in[2]] ; #DOUT2 P30_P3 JC1_2_P
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports adc_data_in[3]] ; #DOUT3 P30_P4 JC1_2_N
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports reset_n] ; #RESET_N P30_P7 JC1_3_P
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports start_n] ; #START_N P30_P1 JC1_1_P
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS33} [get_ports sdp_convst] ; #CONVST P30_P8 JC1_3_N
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS33} [get_ports alert] ; #ALERT P16_P1 JB1_1
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports sync_adc_miso] ; #SYNC_OUT_N P16_P2 JB1_2
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports sync_adc_mosi] ; #SYNC_IN_N P16_P3 JB1_3
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports gpio0] ; #GPIO0 P16_P7 JB1_7
set_property -dict {PACKAGE_PIN W10 IOSTANDARD LVCMOS33} [get_ports gpio1] ; #GPIO1 P16_P8 JB1_8
set_property -dict {PACKAGE_PIN V9 IOSTANDARD LVCMOS33} [get_ports gpio2] ; #GPIO2 P16_P9 JB1_9
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS33} [get_ports sdp_mclk] ; #EXT_MCLK? P24_P7 JA1_7
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_csn] ; #CS_N P24_P1 JA1_1
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_mosi] ; #SDI P24_P2 JA1_2
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi_miso] ; #SDO P24_P3 JA1_3
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; #SCLK P24_P4 JA1_4
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets adc_clk_in]
create_clock -name adc_clk -period 488 [get_ports adc_clk_in]
set fall_min 224; # period/2(=244) - skew_bfe(=20)
set fall_max 264; # period/2(=244) + skew_are(=20)
set_input_delay -clock adc_clk -max $fall_max [get_ports adc_data_in[*]] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports adc_data_in[*]] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports adc_ready_in ] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports adc_ready_in ] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports sync_adc_miso ] -clock_fall -add_delay;
set_input_delay -clock adc_clk -min $fall_min [get_ports sync_adc_miso ] -clock_fall -add_delay;

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# load script
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad777x_ardz_zed 0
adi_project_files ad777x_ardz_zed [list \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" ]
adi_project_run ad777x_ardz_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// adc interface
input adc_clk_in,
input adc_ready_in,
input [ 3:0] adc_data_in,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso,
output start_n,
output sync_adc_mosi,
input sync_adc_miso,
input alert,
output sdp_convst,
output sdp_mclk,
output reset_n,
inout gpio0,
inout gpio1,
inout gpio2,
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// gpio assign
assign gpio_i[32] = alert;
assign start_n = gpio_o[33];
assign sdp_convst = gpio_o[34];
assign sdp_mclk = gpio_o[35];
assign reset_n = gpio_o[39];
assign gpio_i[63:39] = gpio_o[63:39];
assign gpio_i[35:33] = gpio_o[35:33];
assign gpio_i[31:15] = gpio_o[31:15];
ad_iobuf #(
.DATA_WIDTH(15)
) iobuf_gpio_bd (
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_t (gpio_t[14:0]),
.dio_p (gpio_bd[14:0]));
ad_iobuf #(
.DATA_WIDTH(3)
) iobuf_gpio_chip (
.dio_i (gpio_o[38:36]),
.dio_o (gpio_i[38:36]),
.dio_t (gpio_t[38:36]),
.dio_p ({
gpio2, //38
gpio1, //37
gpio0})); //36
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
.dio_p (iic_mux_sda));
system_wrapper i_system_wrapper (
.adc_clk_in(adc_clk_in),
.adc_ready(adc_ready_in),
.adc_data_in(adc_data_in),
.sync_adc_mosi(sync_adc_mosi),
.sync_adc_miso(sync_adc_miso),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o ());
endmodule