diff --git a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
index 2293da93e..d775f0a42 100644
--- a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016, 2018, 2019, 2020, 2021, 2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
index 7cddda987..41487aa70 100644
--- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
index 3540c1ba9..268a26309 100644
--- a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
+++ b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
index c45c758bb..b4c37e6a1 100644
--- a/library/intel/jesd204_phy/jesd204_phy_hw.tcl
+++ b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/README.md b/library/jesd204/README.md
index 53cdc577f..1022c9998 100644
--- a/library/jesd204/README.md
+++ b/library/jesd204/README.md
@@ -8,7 +8,7 @@ different than all other HDL cores in this repository.
 Please read this, and understand the freedoms and responsibilities you have by
 using this source code/core.
 
-The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
 
 This core is free software, you can use run, copy, study, change, ask questions
 about and improve this core. Distribution of source, or resulting binaries
@@ -41,7 +41,7 @@ or publication in which you use this JESD204 HDL core. (You are not required to
 do so; it is up to your common sense to decide whether you want to comply with
 this request or not.) For general publications, we suggest referencing : “The
 design and implementation of the JESD204 HDL Core used in this project is
-copyright © 2016-2017, Analog Devices, Inc.”
+copyright © 2016-2023, Analog Devices, Inc.”
 
 ## Support
 
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
index 02d6079e4..6a4a84baf 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
@@ -1,25 +1,7 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
-#
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
-#
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
-#
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
-#
-# OR
-#
-#   2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
-#
-# ***************************************************************************
-# ***************************************************************************
+###############################################################################
+## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
index babf53718..cb407b48a 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
@@ -1,25 +1,7 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
-#
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
-#
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
-#
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
-#
-# OR
-#
-#   2. An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
-#
-# ***************************************************************************
-# ***************************************************************************
+###############################################################################
+## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
index 0964d8d33..60e13634c 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
@@ -1,25 +1,7 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
-#
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
-#
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
-#
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
-#
-# OR
-#
-#   2. An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
-#
-# ***************************************************************************
-# ***************************************************************************
+###############################################################################
+## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
@@ -501,7 +483,7 @@ proc p_ad_ip_jesd204_tpl_dac_elab {} {
   set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"]
 
   # The DMA interface is rounded to nearest power of two bytes per sample,
-  # e.g NP=12 is padded into 16 bits 
+  # e.g NP=12 is padded into 16 bits
   set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))]
   set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS]
 
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
index c24f7ccf7..d1248de0f 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
@@ -1,25 +1,7 @@
-# ***************************************************************************
-# ***************************************************************************
-# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
-#
-# Each core or library found in this collection may have its own licensing terms.
-# The user should keep this in in mind while exploring these cores.
-#
-# Redistribution and use in source and binary forms,
-# with or without modification of this file, are permitted under the terms of either
-#  (at the option of the user):
-#
-#   1. The GNU General Public License version 2 as published by the
-#      Free Software Foundation, which can be found in the top level directory, or at:
-# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
-#
-# OR
-#
-#   2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
-# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
-#
-# ***************************************************************************
-# ***************************************************************************
+###############################################################################
+## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py b/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
index 84899c029..62ad6017e 100755
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
@@ -1,5 +1,10 @@
 #!/usr/bin/env python3
 
+###############################################################################
+## Copyright (C) 2018 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
 import math
 import os
 import sys
diff --git a/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
index e9478bd7c..3d7d74b6c 100644
--- a/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
+++ b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016, 2017, 2019, 2022, 2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
index c0f6c58e8..fe22bcb79 100755
--- a/library/jesd204/axi_jesd204_common/jesd204_up_common.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
index 141588919..9c624922d 100755
--- a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
index 899d14aa5..33ab3424f 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
index 1bfee9f12..0b9c16f9e 100644
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
index 64016d772..aa6023365 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2018, 2020-2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set core_clk [get_clocks -of_objects [get_ports core_clk]]
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
index 1f382f813..836d06381 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
index 3d5f21300..377e6390a 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
index f0b39278f..a6e0680ff 100644
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
index 9663395b7..dd3815d22 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
index 499bfe91b..29eecfa67 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
index 3663dc750..649b75470 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
index 7953c4954..fd201f10e 100755
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
index 1335ef662..3e51e1ee5 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
index 63fb3fe17..9d51f20c1 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set core_clk [get_clocks -of_objects [get_ports core_clk]]
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
index 802316781..50ad24af4 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
index 7ec5f47a1..0675d48d2 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
index f0b39278f..a6e0680ff 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
index 1596f0cba..699db5195 100755
--- a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
+++ b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/interfaces/interfaces_ip.tcl b/library/jesd204/interfaces/interfaces_ip.tcl
index dac4f935e..c8300beb2 100755
--- a/library/jesd204/interfaces/interfaces_ip.tcl
+++ b/library/jesd204/interfaces/interfaces_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_common/jesd204_common_ip.tcl b/library/jesd204/jesd204_common/jesd204_common_ip.tcl
index 3e245a02d..afd58a7dc 100755
--- a/library/jesd204/jesd204_common/jesd204_common_ip.tcl
+++ b/library/jesd204/jesd204_common/jesd204_common_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_common/jesd204_crc12.v b/library/jesd204/jesd204_common/jesd204_crc12.v
index 0cd320ec7..85a9d4ecd 100644
--- a/library/jesd204/jesd204_common/jesd204_crc12.v
+++ b/library/jesd204/jesd204_common/jesd204_crc12.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_eof_generator.v b/library/jesd204/jesd204_common/jesd204_eof_generator.v
index bd92ae2cb..03cb7c216 100644
--- a/library/jesd204/jesd204_common/jesd204_eof_generator.v
+++ b/library/jesd204/jesd204_common/jesd204_eof_generator.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
index 152ab638b..41e1a653c 100755
--- a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
+++ b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 // Limitations:
 //   DATA_PATH_WIDTH = 4, 8
diff --git a/library/jesd204/jesd204_common/jesd204_frame_mark.v b/library/jesd204/jesd204_common/jesd204_frame_mark.v
index a92a880a4..b6cee5e3b 100755
--- a/library/jesd204/jesd204_common/jesd204_frame_mark.v
+++ b/library/jesd204/jesd204_common/jesd204_frame_mark.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 // Limitations:
 //  for DATA_PATH_WIDTH = 4, 8
diff --git a/library/jesd204/jesd204_common/jesd204_lmfc.v b/library/jesd204/jesd204_common/jesd204_lmfc.v
index 9b3d9fe1e..1a6aee8f8 100755
--- a/library/jesd204/jesd204_common/jesd204_lmfc.v
+++ b/library/jesd204/jesd204_common/jesd204_lmfc.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_scrambler.v b/library/jesd204/jesd204_common/jesd204_scrambler.v
index 91f5cc83a..681dd560b 100644
--- a/library/jesd204/jesd204_common/jesd204_scrambler.v
+++ b/library/jesd204/jesd204_common/jesd204_scrambler.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
index 6b8eaf312..7dbc8d497 100644
--- a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
+++ b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v
index 325698d61..37108cf42 100644
--- a/library/jesd204/jesd204_common/pipeline_stage.v
+++ b/library/jesd204/jesd204_common/pipeline_stage.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/sync_header_align.v b/library/jesd204/jesd204_common/sync_header_align.v
index e2af2958c..546ef4ce2 100644
--- a/library/jesd204/jesd204_common/sync_header_align.v
+++ b/library/jesd204/jesd204_common/sync_header_align.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/align_mux.v b/library/jesd204/jesd204_rx/align_mux.v
index b328a7a71..455d7a87f 100755
--- a/library/jesd204/jesd204_rx/align_mux.v
+++ b/library/jesd204/jesd204_rx/align_mux.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/bd/bd.tcl b/library/jesd204/jesd204_rx/bd/bd.tcl
index 7394bb17a..d8d7739ae 100644
--- a/library/jesd204/jesd204_rx/bd/bd.tcl
+++ b/library/jesd204/jesd204_rx/bd/bd.tcl
@@ -1,3 +1,8 @@
+###############################################################################
+## Copyright (C) 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
 proc init {cellpath otherInfo} {
   set ip [get_bd_cells $cellpath]
 
diff --git a/library/jesd204/jesd204_rx/elastic_buffer.v b/library/jesd204/jesd204_rx/elastic_buffer.v
index de1029740..87ca4a5cf 100644
--- a/library/jesd204/jesd204_rx/elastic_buffer.v
+++ b/library/jesd204/jesd204_rx/elastic_buffer.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/error_monitor.v b/library/jesd204/jesd204_rx/error_monitor.v
index 4fec2b948..421206f42 100644
--- a/library/jesd204/jesd204_rx/error_monitor.v
+++ b/library/jesd204/jesd204_rx/error_monitor.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
index 5629bdc1f..8ecd95880 100755
--- a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
+++ b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
index 93db35b76..b72840743 100755
--- a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
+++ b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx.v b/library/jesd204/jesd204_rx/jesd204_rx.v
index 37990979c..00602c5c3 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
index 9753d5590..ee88ce6cb 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc b/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
index b2015d205..14c4731b2 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
+++ b/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017, 2020, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl b/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
index 0af17726c..00c39fda0 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
@@ -1,46 +1,8 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
 <: set ComponentName [getComponentNameString] :>
 <: setOutputDirectory "./" :>
 <: setFileName [ttcl_add $ComponentName "_constr"] :>
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
index e04085fd1..a032b92a0 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
index 0e5f89738..9fa08355b 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v b/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
index 6dbf943da..fafd87b47 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_header.v b/library/jesd204/jesd204_rx/jesd204_rx_header.v
index 3fd1e6d9f..14e34e32a 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_header.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_header.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
index 1f6eaf8c5..4186ddb13 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl b/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
index 33757b57d..023c893b5 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane.v b/library/jesd204/jesd204_rx/jesd204_rx_lane.v
index 048304c99..277cb6486 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_lane.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_lane.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v b/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
index 17736d940..fea5aeaaf 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl b/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl
index fd5744727..3eba1ddb0 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl
@@ -1,25 +1,7 @@
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
index 26e9256c5..8c721bed9 100755
--- a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
+++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl
index 17f179382..a21e8741e 100755
--- a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl
+++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
index 745eab54d..c9cb8c921 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
index 48ea174d1..0ccfd1ce6 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
index b803904c9..2da67b43b 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
index 2d5a21fb6..2995ba2ec 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
index eb0e9e707..4c12c8ade 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
index d22a1ae72..870054b69 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
index 1e4dcc5c7..8e84d44a9 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_tx/bd/bd.tcl b/library/jesd204/jesd204_tx/bd/bd.tcl
index 7394bb17a..d8d7739ae 100644
--- a/library/jesd204/jesd204_tx/bd/bd.tcl
+++ b/library/jesd204/jesd204_tx/bd/bd.tcl
@@ -1,3 +1,8 @@
+###############################################################################
+## Copyright (C) 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
 proc init {cellpath otherInfo} {
   set ip [get_bd_cells $cellpath]
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx.v b/library/jesd204/jesd204_tx/jesd204_tx.v
index 73d323bcb..a0bf699e1 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc b/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
index ba2c4961e..bb3ab5c20 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
+++ b/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl b/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
index 328abb531..53f689630 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
@@ -1,46 +1,8 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
 <: set ComponentName [getComponentNameString] :>
 <: setOutputDirectory "./" :>
 <: setFileName [ttcl_add $ComponentName "_constr"] :>
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
index 3fe5800dc..94e06a0bc 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v b/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
index 724275ba8..9956c0c08 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_header.v b/library/jesd204/jesd204_tx/jesd204_tx_header.v
index c3a08c5b3..a4269b350 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_header.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_header.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
index ede6b0277..b852dceb5 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
index e17debf8b..ab491bc90 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane.v b/library/jesd204/jesd204_tx/jesd204_tx_lane.v
index 261fc68ab..8fb6bf27c 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx_lane.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
index 289d8c113..eb2e293f1 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl b/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl
index fd5744727..3eba1ddb0 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl
@@ -1,25 +1,7 @@
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
index 7e0ade95f..7335b6c93 100755
--- a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
index 848f90a0a..fd7add3f0 100755
--- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl
index f8308e49b..89106acfc 100644
--- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
index fe6b4df4a..0b6304059 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
index 15d18f8ed..b2f37d867 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
index 4b98d250f..21a53145d 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
index 57e9db9ca..04fbb5847 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/scripts/jesd204.tcl b/library/jesd204/scripts/jesd204.tcl
index c94fc6d5a..d2a3e6645 100644
--- a/library/jesd204/scripts/jesd204.tcl
+++ b/library/jesd204/scripts/jesd204.tcl
@@ -1,46 +1,7 @@
-#
-# The ADI JESD204 Core is released under the following license, which is
-# different than all other HDL cores in this repository.
-#
-# Please read this, and understand the freedoms and responsibilities you have
-# by using this source code/core.
-#
-# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-#
-# This core is free software, you can use run, copy, study, change, ask
-# questions about and improve this core. Distribution of source, or resulting
-# binaries (including those inside an FPGA or ASIC) require you to release the
-# source of the entire project (excluding the system libraries provide by the
-# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-# License version 2 as published by the Free Software Foundation.
-#
-# This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License version 2
-# along with this source code, and binary.  If not, see
-# <http://www.gnu.org/licenses/>.
-#
-# Commercial licenses (with commercial support) of this JESD204 core are also
-# available under terms different than the General Public License. (e.g. they
-# do not require you to accompany any image (FPGA or ASIC) using the JESD204
-# core with any corresponding source code.) For these alternate terms you must
-# purchase a license from Analog Devices Technology Licensing Office. Users
-# interested in such a license should contact jesd204-licensing@analog.com for
-# more information. This commercial license is sub-licensable (if you purchase
-# chips from Analog Devices, incorporate them into your PCB level product, and
-# purchase a JESD204 license, end users of your product will also have a
-# license to use this core in a commercial setting without releasing their
-# source code).
-#
-# In addition, we kindly ask you to acknowledge ADI in any program, application
-# or publication in which you use this JESD204 HDL core. (You are not required
-# to do so; it is up to your common sense to decide whether you want to comply
-# with this request or not.) For general publications, we suggest referencing :
-# “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2017, Analog Devices, Inc.”
-#
+###############################################################################
+## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
 
 proc adi_axi_jesd204_tx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
 
diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
index 46ab4503c..9ac30bdd8 100644
--- a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
index f3b684b7b..49408390f 100644
--- a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/crc12_tb.v b/library/jesd204/tb/crc12_tb.v
index 56d1979c0..74e413f10 100644
--- a/library/jesd204/tb/crc12_tb.v
+++ b/library/jesd204/tb/crc12_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/frame_align_tb.v b/library/jesd204/tb/frame_align_tb.v
index 05a61918a..171ba5bce 100755
--- a/library/jesd204/tb/frame_align_tb.v
+++ b/library/jesd204/tb/frame_align_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// �The design and implementation of the JESD204 HDL Core used in this project
-// is copyright � 2016-2017, Analog Devices, Inc.�
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/jesd204_frame_align_replace_tb.v b/library/jesd204/tb/jesd204_frame_align_replace_tb.v
index b84aca1d6..5ba5e76be 100755
--- a/library/jesd204/tb/jesd204_frame_align_replace_tb.v
+++ b/library/jesd204/tb/jesd204_frame_align_replace_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/jesd204_frame_mark_tb.v b/library/jesd204/tb/jesd204_frame_mark_tb.v
index 7a05d8a36..c1925511c 100755
--- a/library/jesd204/tb/jesd204_frame_mark_tb.v
+++ b/library/jesd204/tb/jesd204_frame_mark_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/loopback_64b_tb.v b/library/jesd204/tb/loopback_64b_tb.v
index c8e845622..7c845cfb6 100644
--- a/library/jesd204/tb/loopback_64b_tb.v
+++ b/library/jesd204/tb/loopback_64b_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/loopback_tb.v b/library/jesd204/tb/loopback_tb.v
index 905e464a9..b0ddd18ba 100755
--- a/library/jesd204/tb/loopback_tb.v
+++ b/library/jesd204/tb/loopback_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_cgs_tb.v b/library/jesd204/tb/rx_cgs_tb.v
index 04cf2dcd5..a0f7212da 100644
--- a/library/jesd204/tb/rx_cgs_tb.v
+++ b/library/jesd204/tb/rx_cgs_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_ctrl_tb.v b/library/jesd204/tb/rx_ctrl_tb.v
index 0f622bcdf..d8546ec34 100644
--- a/library/jesd204/tb/rx_ctrl_tb.v
+++ b/library/jesd204/tb/rx_ctrl_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_lane_tb.v b/library/jesd204/tb/rx_lane_tb.v
index 9eb77de2b..e3d5d0c6b 100644
--- a/library/jesd204/tb/rx_lane_tb.v
+++ b/library/jesd204/tb/rx_lane_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_tb.v b/library/jesd204/tb/rx_tb.v
index cbeee37c6..7dba6cc8a 100644
--- a/library/jesd204/tb/rx_tb.v
+++ b/library/jesd204/tb/rx_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/scrambler_64b_tb.v b/library/jesd204/tb/scrambler_64b_tb.v
index 8358f0f8d..8310a0914 100644
--- a/library/jesd204/tb/scrambler_64b_tb.v
+++ b/library/jesd204/tb/scrambler_64b_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/scrambler_tb.v b/library/jesd204/tb/scrambler_tb.v
index b2e93a0b8..a46bfdb43 100644
--- a/library/jesd204/tb/scrambler_tb.v
+++ b/library/jesd204/tb/scrambler_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
index dab6c5c5b..5a1ade874 100644
--- a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
+++ b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
index 43533110a..6a1b1aa82 100644
--- a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
+++ b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_loopback_tb.v b/library/jesd204/tb/soft_pcs_loopback_tb.v
index a86743ec2..8204bb34a 100644
--- a/library/jesd204/tb/soft_pcs_loopback_tb.v
+++ b/library/jesd204/tb/soft_pcs_loopback_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A pcsTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_pattern_align_tb.v b/library/jesd204/tb/soft_pcs_pattern_align_tb.v
index 1902040ad..53c0b6876 100644
--- a/library/jesd204/tb/soft_pcs_pattern_align_tb.v
+++ b/library/jesd204/tb/soft_pcs_pattern_align_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/tb_base.v b/library/jesd204/tb/tb_base.v
index 87df5b171..66086779f 100755
--- a/library/jesd204/tb/tb_base.v
+++ b/library/jesd204/tb/tb_base.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2019, 2020, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;
diff --git a/library/jesd204/tb/tx_64b_tb.v b/library/jesd204/tb/tx_64b_tb.v
index 9d4aaa655..4a9eb1bc0 100644
--- a/library/jesd204/tb/tx_64b_tb.v
+++ b/library/jesd204/tb/tx_64b_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/tx_ctrl_phase_tb.v b/library/jesd204/tb/tx_ctrl_phase_tb.v
index 9c5b60dcf..f78a71754 100644
--- a/library/jesd204/tb/tx_ctrl_phase_tb.v
+++ b/library/jesd204/tb/tx_ctrl_phase_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 /*
  * Regardless of the phase relationship between LMFC and sync the output of the
diff --git a/library/jesd204/tb/tx_tb.v b/library/jesd204/tb/tx_tb.v
index b3ff94a99..cb901f14d 100644
--- a/library/jesd204/tb/tx_tb.v
+++ b/library/jesd204/tb/tx_tb.v
@@ -1,46 +1,9 @@
-//
-// The ADI JESD204 Core is released under the following license, which is
-// different than all other HDL cores in this repository.
-//
-// Please read this, and understand the freedoms and responsibilities you have
-// by using this source code/core.
-//
-// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
-//
-// This core is free software, you can use run, copy, study, change, ask
-// questions about and improve this core. Distribution of source, or resulting
-// binaries (including those inside an FPGA or ASIC) require you to release the
-// source of the entire project (excluding the system libraries provide by the
-// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
-// License version 2 as published by the Free Software Foundation.
-//
-// This core  is distributed in the hope that it will be useful, but WITHOUT ANY
-// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
-// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License version 2
-// along with this source code, and binary.  If not, see
-// <http://www.gnu.org/licenses/>.
-//
-// Commercial licenses (with commercial support) of this JESD204 core are also
-// available under terms different than the General Public License. (e.g. they
-// do not require you to accompany any image (FPGA or ASIC) using the JESD204
-// core with any corresponding source code.) For these alternate terms you must
-// purchase a license from Analog Devices Technology Licensing Office. Users
-// interested in such a license should contact jesd204-licensing@analog.com for
-// more information. This commercial license is sub-licensable (if you purchase
-// chips from Analog Devices, incorporate them into your PCB level product, and
-// purchase a JESD204 license, end users of your product will also have a
-// license to use this core in a commercial setting without releasing their
-// source code).
-//
-// In addition, we kindly ask you to acknowledge ADI in any program, application
-// or publication in which you use this JESD204 HDL core. (You are not required
-// to do so; it is up to your common sense to decide whether you want to comply
-// with this request or not.) For general publications, we suggest referencing :
-// “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2017, Analog Devices, Inc.”
-//
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
+// SPDX short identifier: ADIJESD204
+// ***************************************************************************
+// ***************************************************************************
 
 `timescale 1ns/100ps