Add copyright & license for all files needing ADI JESD specific license
* Added every year when the file was edited, with comma * Range if it's consecutive years Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>main
Iulia Moldovan
imoldovan
parent
49cf0f7ae3
commit
0590a4046c
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@ -1,46 +1,7 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
|
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# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
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# source of the entire project (excluding the system libraries provide by the
|
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
|
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
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# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
|
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# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
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||||
# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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###############################################################################
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## Copyright (C) 2016, 2018, 2019, 2020, 2021, 2022 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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source ../../../scripts/adi_env.tcl
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@ -1,46 +1,7 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
|
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
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# source of the entire project (excluding the system libraries provide by the
|
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
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# You should have received a copy of the GNU General Public License version 2
|
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# along with this source code, and binary. If not, see
|
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# <http://www.gnu.org/licenses/>.
|
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
|
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# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
|
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# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
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# purchase a JESD204 license, end users of your product will also have a
|
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
|
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# or publication in which you use this JESD204 HDL core. (You are not required
|
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# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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###############################################################################
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## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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source ../../../scripts/adi_env.tcl
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@ -1,46 +1,7 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
|
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# by using this source code/core.
|
||||
#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
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# License version 2 as published by the Free Software Foundation.
|
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#
|
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
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# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
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# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
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# source code).
|
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
|
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# or publication in which you use this JESD204 HDL core. (You are not required
|
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# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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###############################################################################
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## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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source ../../../scripts/adi_env.tcl
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@ -1,46 +1,7 @@
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#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
|
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# by using this source code/core.
|
||||
#
|
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
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#
|
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# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
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# License version 2 as published by the Free Software Foundation.
|
||||
#
|
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
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# Commercial licenses (with commercial support) of this JESD204 core are also
|
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# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
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# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
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#
|
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# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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###############################################################################
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## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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@ -8,7 +8,7 @@ different than all other HDL cores in this repository.
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Please read this, and understand the freedoms and responsibilities you have by
|
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using this source code/core.
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||||
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The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
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The JESD204 HDL, is copyright © 2016-2023 Analog Devices Inc.
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This core is free software, you can use run, copy, study, change, ask questions
|
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about and improve this core. Distribution of source, or resulting binaries
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|
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@ -41,7 +41,7 @@ or publication in which you use this JESD204 HDL core. (You are not required to
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do so; it is up to your common sense to decide whether you want to comply with
|
||||
this request or not.) For general publications, we suggest referencing : “The
|
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design and implementation of the JESD204 HDL Core used in this project is
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copyright © 2016-2017, Analog Devices, Inc.”
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copyright © 2016-2023, Analog Devices, Inc.”
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## Support
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@ -1,25 +1,7 @@
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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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#
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# Each core or library found in this collection may have its own licensing terms.
|
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# The user should keep this in in mind while exploring these cores.
|
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#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
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# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
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# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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#
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# OR
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#
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# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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#
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# ***************************************************************************
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# ***************************************************************************
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###############################################################################
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## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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source ../../../scripts/adi_env.tcl
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@ -1,25 +1,7 @@
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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
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#
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# Each core or library found in this collection may have its own licensing terms.
|
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# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
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# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
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# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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#
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# OR
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#
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# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
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# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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#
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# ***************************************************************************
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# ***************************************************************************
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###############################################################################
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## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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@ -1,25 +1,7 @@
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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
#
|
||||
# Each core or library found in this collection may have its own licensing terms.
|
||||
# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
||||
# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
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# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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#
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# OR
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#
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# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
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#
|
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# ***************************************************************************
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# ***************************************************************************
|
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###############################################################################
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## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
|
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### SPDX short identifier: ADIJESD204
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###############################################################################
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package require qsys 14.0
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source ../../../scripts/adi_env.tcl
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@ -501,7 +483,7 @@ proc p_ad_ip_jesd204_tpl_dac_elab {} {
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set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"]
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# The DMA interface is rounded to nearest power of two bytes per sample,
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# e.g NP=12 is padded into 16 bits
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# e.g NP=12 is padded into 16 bits
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set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))]
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set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS]
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@ -1,25 +1,7 @@
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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
|
||||
#
|
||||
# Each core or library found in this collection may have its own licensing terms.
|
||||
# The user should keep this in in mind while exploring these cores.
|
||||
#
|
||||
# Redistribution and use in source and binary forms,
|
||||
# with or without modification of this file, are permitted under the terms of either
|
||||
# (at the option of the user):
|
||||
#
|
||||
# 1. The GNU General Public License version 2 as published by the
|
||||
# Free Software Foundation, which can be found in the top level directory, or at:
|
||||
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
||||
#
|
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# OR
|
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#
|
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# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
||||
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
||||
#
|
||||
# ***************************************************************************
|
||||
# ***************************************************************************
|
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###############################################################################
|
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## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
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###############################################################################
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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@ -1,5 +1,10 @@
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#!/usr/bin/env python3
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###############################################################################
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## Copyright (C) 2018 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIJESD204
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###############################################################################
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import math
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import os
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import sys
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@ -1,46 +1,7 @@
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#
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||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016, 2017, 2019, 2022, 2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2018, 2020-2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set core_clk [get_clocks -of_objects [get_ports core_clk]]
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set core_clk [get_clocks -of_objects [get_ports core_clk]]
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
// Limitations:
|
||||
// DATA_PATH_WIDTH = 4, 8
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
// Limitations:
|
||||
// for DATA_PATH_WIDTH = 4, 8
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
###############################################################################
|
||||
## Copyright (C) 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017, 2020, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,8 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,25 +1,7 @@
|
|||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
###############################################################################
|
||||
## Copyright (C) 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,8 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
package require qsys 14.0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,25 +1,7 @@
|
|||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
|
|
|||
|
|
@ -1,46 +1,7 @@
|
|||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact jesd204-licensing@analog.com for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
###############################################################################
|
||||
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
### SPDX short identifier: ADIJESD204
|
||||
###############################################################################
|
||||
|
||||
proc adi_axi_jesd204_tx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
|
|
@ -1,46 +1,9 @@
|
|||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact jesd204-licensing@analog.com for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
|
||||
// SPDX short identifier: ADIJESD204
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue