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fmcjesdadc1: a10soc

main
Rejeesh Kutty 2017-06-13 15:00:22 -04:00
parent c1bc1259a7
commit 051c1d6644
5 changed files with 676 additions and 0 deletions
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projects/fmcjesdadc1/a10soc/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
ifeq ($(NIOS2_MMU),)
NIOS2_MMU := 1
endif
export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU)
M_DEPS += system_top.v
M_DEPS += system_qsys.tcl
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += ../common/adrv9371x_qsys.tcl
M_DEPS += ../../scripts/adi_tquest.tcl
M_DEPS += ../../scripts/adi_project_alt.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
M_DEPS += ../../common/a10soc/a10soc_plddr4_assign.tcl
M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_byteenable_coder.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_byteenable_decoder.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_constr.sdc
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_hw.tcl
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_rd.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_wr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
M_DEPS += ../../../library/altera/common/ad_dcfilter.v
M_DEPS += ../../../library/altera/common/ad_mem_asym.v
M_DEPS += ../../../library/altera/common/ad_mul.v
M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
M_DEPS += ../../../library/axi_ad9371/axi_ad9371.v
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_hw.tcl
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_if.v
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx.v
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_channel.v
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_rx_os.v
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx.v
M_DEPS += ../../../library/axi_ad9371/axi_ad9371_tx_channel.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_axis_inf_rx.v
M_DEPS += ../../../library/common/ad_b2g.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_g2b.v
M_DEPS += ../../../library/common/ad_iqcor.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/common/util_dacfifo_bypass.v
M_DEPS += ../../../library/common/util_delay.v
M_DEPS += ../../../library/scripts/adi_env.tcl
M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf
.PHONY: all clean clean-all
all: adrv9371x_a10soc.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
adrv9371x_a10soc.sof: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> adrv9371x_a10soc_quartus.log 2>&1
####################################################################################
####################################################################################

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projects/fmcjesdadc1/a10soc/system_constr.sdc Normal file
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# qsys- automatically infers these clocks
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
derive_pll_clocks
derive_clock_uncertainty
set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*]
set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*]
set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]

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source ../../scripts/adi_env.tcl
source ../../scripts/adi_project_alt.tcl
adi_project_altera adrv9371x_a10soc
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_assign.tcl
# ad9371
set_location_assignment PIN_N29 -to ref_clk0 ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
set_location_assignment PIN_N28 -to "ref_clk0(n)" ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
set_location_assignment PIN_R29 -to ref_clk1 ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_location_assignment PIN_R28 -to "ref_clk1(n)" ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_location_assignment PIN_R33 -to rx_data[0] ; ## A02 FMC_HPC_DP1_M2C_P
set_location_assignment PIN_R32 -to "rx_data[0](n)" ; ## A03 FMC_HPC_DP1_M2C_N
set_location_assignment PIN_P35 -to rx_data[1] ; ## A06 FMC_HPC_DP2_M2C_P
set_location_assignment PIN_P34 -to "rx_data[1](n)" ; ## A07 FMC_HPC_DP2_M2C_N
set_location_assignment PIN_T31 -to rx_data[2] ; ## C06 FMC_HPC_DP0_M2C_P
set_location_assignment PIN_T30 -to "rx_data[2](n)" ; ## C07 FMC_HPC_DP0_M2C_N
set_location_assignment PIN_P31 -to rx_data[3] ; ## A10 FMC_HPC_DP3_M2C_P
set_location_assignment PIN_P30 -to "rx_data[3](n)" ; ## A11 FMC_HPC_DP3_M2C_N
set_location_assignment PIN_M39 -to tx_data[0] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[3])
set_location_assignment PIN_M38 -to "tx_data[0](n)" ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[3])
set_location_assignment PIN_L37 -to tx_data[1] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[0])
set_location_assignment PIN_L36 -to "tx_data[1](n)" ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[0])
set_location_assignment PIN_N37 -to tx_data[2] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[1])
set_location_assignment PIN_N36 -to "tx_data[2](n)" ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[1])
set_location_assignment PIN_K39 -to tx_data[3] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[2])
set_location_assignment PIN_K38 -to "tx_data[3](n)" ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[2])
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk0
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk1
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data
set_instance_assignment -name IO_STANDARD LVDS -to ref_clk0
set_instance_assignment -name IO_STANDARD LVDS -to ref_clk1
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
set_location_assignment PIN_C14 -to rx_sync ; ## G09 FMC_HPC_LA03_P
set_location_assignment PIN_D14 -to rx_sync(n) ; ## G10 FMC_HPC_LA03_N
set_location_assignment PIN_E3 -to rx_os_sync ; ## G27 FMC_HPC_LA25_P (Sniffer)
set_location_assignment PIN_F3 -to rx_os_sync(n) ; ## G28 FMC_HPC_LA25_N (Sniffer)
set_location_assignment PIN_C13 -to tx_sync ; ## H07 FMC_HPC_LA02_P
set_location_assignment PIN_D13 -to tx_sync(n) ; ## H08 FMC_HPC_LA02_N
set_location_assignment PIN_P11 -to sysref ; ## G36 FMC_HPC_LA33_P
set_location_assignment PIN_R11 -to sysref(n) ; ## G37 FMC_HPC_LA33_N
set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
set_instance_assignment -name IO_STANDARD LVDS -to rx_os_sync
set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
set_instance_assignment -name IO_STANDARD LVDS -to sysref
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sysref
set_location_assignment PIN_A13 -to spi_csn_ad9528 ; ## D15 FMC_HPC_LA09_N
set_location_assignment PIN_A12 -to spi_csn_ad9371 ; ## D14 FMC_HPC_LA09_P
set_location_assignment PIN_A9 -to spi_clk ; ## H13 FMC_HPC_LA07_P
set_location_assignment PIN_B9 -to spi_mosi ; ## H14 FMC_HPC_LA07_N
set_location_assignment PIN_B11 -to spi_miso ; ## G12 FMC_HPC_LA08_P
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9528
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_ad9371
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_mosi
set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_miso
set_location_assignment PIN_F2 -to ad9528_reset_b ; ## D26 FMC_HPC_LA26_P
set_location_assignment PIN_G2 -to ad9528_sysref_req ; ## D27 FMC_HPC_LA26_N
set_location_assignment PIN_J11 -to ad9371_tx1_enable ; ## D17 FMC_HPC_LA13_P
set_location_assignment PIN_J9 -to ad9371_tx2_enable ; ## C18 FMC_HPC_LA14_P
set_location_assignment PIN_K11 -to ad9371_rx1_enable ; ## D18 FMC_HPC_LA13_N
set_location_assignment PIN_J10 -to ad9371_rx2_enable ; ## C19 FMC_HPC_LA14_N
set_location_assignment PIN_F13 -to ad9371_test ; ## D11 FMC_HPC_LA05_P (DNI/NC)
set_location_assignment PIN_H12 -to ad9371_reset_b ; ## H10 FMC_HPC_LA04_P
set_location_assignment PIN_H13 -to ad9371_gpint ; ## H11 FMC_HPC_LA04_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_reset_b
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9528_sysref_req
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx1_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_tx2_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx1_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_rx2_enable
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_test
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_reset_b
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpint
# single ended default
set_location_assignment PIN_D4 -to ad9371_gpio[0] ; ## H19 FMC_HPC_LA15_P
set_location_assignment PIN_D5 -to ad9371_gpio[1] ; ## H20 FMC_HPC_LA15_N
set_location_assignment PIN_D6 -to ad9371_gpio[2] ; ## G18 FMC_HPC_LA16_P
set_location_assignment PIN_E6 -to ad9371_gpio[3] ; ## G19 FMC_HPC_LA16_N
set_location_assignment PIN_C2 -to ad9371_gpio[4] ; ## H25 FMC_HPC_LA21_P
set_location_assignment PIN_D3 -to ad9371_gpio[5] ; ## H26 FMC_HPC_LA21_N
set_location_assignment PIN_G7 -to ad9371_gpio[6] ; ## C22 FMC_HPC_LA18_CC_P
set_location_assignment PIN_H7 -to ad9371_gpio[7] ; ## C23 FMC_HPC_LA18_CC_N
set_location_assignment PIN_G4 -to ad9371_gpio[8] ; ## G25 FMC_HPC_LA22_N (LVDS_1N)
set_location_assignment PIN_G5 -to ad9371_gpio[9] ; ## H22 FMC_HPC_LA19_P (LVDS_2P)
set_location_assignment PIN_G6 -to ad9371_gpio[10] ; ## H23 FMC_HPC_LA19_N (LVDS_2N)
set_location_assignment PIN_C3 -to ad9371_gpio[11] ; ## G21 FMC_HPC_LA20_P (LVDS_3P)
set_location_assignment PIN_C4 -to ad9371_gpio[12] ; ## G22 FMC_HPC_LA20_N (LVDS_3N)
set_location_assignment PIN_P10 -to ad9371_gpio[13] ; ## G31 FMC_HPC_LA29_N (LVDS_4N)
set_location_assignment PIN_N9 -to ad9371_gpio[14] ; ## G30 FMC_HPC_LA29_P (LVDS_4P)
set_location_assignment PIN_F4 -to ad9371_gpio[15] ; ## G24 FMC_HPC_LA22_P (LVDS_1P)
set_location_assignment PIN_N13 -to ad9371_gpio[16] ; ## G16 FMC_HPC_LA12_N (LVDS_5N)
set_location_assignment PIN_M12 -to ad9371_gpio[17] ; ## G15 FMC_HPC_LA12_P (LVDS_5P)
set_location_assignment PIN_F14 -to ad9371_gpio[18] ; ## D12 FMC_HPC_LA05_N
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[11]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[12]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[16]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[17]
set_instance_assignment -name IO_STANDARD "1.8 V" -to ad9371_gpio[18]
execute_flow -compile

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set dac_fifo_name avl_ad9371_tx_fifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl
source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
source ../common/adrv9371x_qsys.tcl

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
input sys_resetn,
// hps-ddr4 (32)
input hps_ddr_ref_clk,
output [ 0:0] hps_ddr_clk_p,
output [ 0:0] hps_ddr_clk_n,
output [ 16:0] hps_ddr_a,
output [ 1:0] hps_ddr_ba,
output [ 0:0] hps_ddr_bg,
output [ 0:0] hps_ddr_cke,
output [ 0:0] hps_ddr_cs_n,
output [ 0:0] hps_ddr_odt,
output [ 0:0] hps_ddr_reset_n,
output [ 0:0] hps_ddr_act_n,
output [ 0:0] hps_ddr_par,
input [ 0:0] hps_ddr_alert_n,
inout [ 3:0] hps_ddr_dqs_p,
inout [ 3:0] hps_ddr_dqs_n,
inout [ 31:0] hps_ddr_dq,
inout [ 3:0] hps_ddr_dbi_n,
input hps_ddr_rzq,
// pl-ddr4
input sys_ddr_ref_clk,
output [ 0:0] sys_ddr_clk_p,
output [ 0:0] sys_ddr_clk_n,
output [ 16:0] sys_ddr_a,
output [ 1:0] sys_ddr_ba,
output [ 0:0] sys_ddr_bg,
output [ 0:0] sys_ddr_cke,
output [ 0:0] sys_ddr_cs_n,
output [ 0:0] sys_ddr_odt,
output [ 0:0] sys_ddr_reset_n,
output [ 0:0] sys_ddr_act_n,
output [ 0:0] sys_ddr_par,
input [ 0:0] sys_ddr_alert_n,
inout [ 7:0] sys_ddr_dqs_p,
inout [ 7:0] sys_ddr_dqs_n,
inout [ 63:0] sys_ddr_dq,
inout [ 7:0] sys_ddr_dbi_n,
input sys_ddr_rzq,
// hps-ethernet
input [ 0:0] hps_eth_rxclk,
input [ 0:0] hps_eth_rxctl,
input [ 3:0] hps_eth_rxd,
output [ 0:0] hps_eth_txclk,
output [ 0:0] hps_eth_txctl,
output [ 3:0] hps_eth_txd,
output [ 0:0] hps_eth_mdc,
inout [ 0:0] hps_eth_mdio,
// hps-sdio
output [ 0:0] hps_sdio_clk,
inout [ 0:0] hps_sdio_cmd,
inout [ 7:0] hps_sdio_d,
// hps-usb
input [ 0:0] hps_usb_clk,
input [ 0:0] hps_usb_dir,
input [ 0:0] hps_usb_nxt,
output [ 0:0] hps_usb_stp,
inout [ 7:0] hps_usb_d,
// hps-uart
input [ 0:0] hps_uart_rx,
output [ 0:0] hps_uart_tx,
// hps-i2c (shared w fmc-a, fmc-b)
inout [ 0:0] hps_i2c_sda,
inout [ 0:0] hps_i2c_scl,
// hps-gpio (max-v-u16)
inout [ 3:0] hps_gpio,
// gpio (max-v-u21)
input [ 7:0] gpio_bd_i,
output [ 3:0] gpio_bd_o,
// ad9371-interface
input ref_clk0,
input ref_clk1,
input [ 3:0] rx_data,
output [ 3:0] tx_data,
output rx_sync,
output rx_os_sync,
input tx_sync,
input sysref,
output ad9528_reset_b,
output ad9528_sysref_req,
output ad9371_tx1_enable,
output ad9371_tx2_enable,
output ad9371_rx1_enable,
output ad9371_rx2_enable,
output ad9371_test,
output ad9371_reset_b,
input ad9371_gpint,
inout [ 18:0] ad9371_gpio,
output spi_csn_ad9528,
output spi_csn_ad9371,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire sys_ddr_cal_success;
wire sys_ddr_cal_fail;
wire sys_hps_resetn;
wire sys_resetn_s;
wire [ 63:0] gpio_i;
wire [ 63:0] gpio_o;
wire [ 7:0] spi_csn_s;
wire dac_fifo_bypass;
// assignments
assign spi_csn_ad9528 = spi_csn_s[0];
assign spi_csn_ad9371 = spi_csn_s[1];
// gpio (ad9371)
assign gpio_i[63:61] = gpio_o[63:61];
assign dac_fifo_bypass = gpio_o[60];
assign gpio_i[60:60] = gpio_o[60];
assign ad9528_reset_b = gpio_o[59];
assign ad9528_sysref_req = gpio_o[58];
assign ad9371_tx1_enable = gpio_o[57];
assign ad9371_tx2_enable = gpio_o[56];
assign ad9371_rx1_enable = gpio_o[55];
assign ad9371_rx2_enable = gpio_o[54];
assign ad9371_test = gpio_o[53];
assign ad9371_reset_b = gpio_o[52];
assign gpio_i[59:52] = gpio_o[59:52];
assign gpio_i[51:51] = ad9371_gpint;
assign gpio_i[50:32] = gpio_o[50:32];
// board stuff (max-v-u21)
assign gpio_i[31:14] = gpio_o[31:14];
assign gpio_i[13:13] = sys_ddr_cal_success;
assign gpio_i[12:12] = sys_ddr_cal_fail;
assign gpio_i[11: 4] = gpio_bd_i;
assign gpio_i[ 3: 0] = gpio_o[3:0];
assign gpio_bd_o = gpio_o[3:0];
// peripheral reset
assign sys_resetn_s = sys_resetn & sys_hps_resetn;
// instantiations
system_bd i_system_bd (
.ad9371_gpio_export (ad9371_gpio),
.rx_data_0_rx_serial_data (rx_data[0]),
.rx_data_1_rx_serial_data (rx_data[1]),
.rx_data_2_rx_serial_data (rx_data[2]),
.rx_data_3_rx_serial_data (rx_data[3]),
.rx_os_ref_clk_clk (ref_clk1),
.rx_os_sync_export (rx_os_sync),
.rx_os_sysref_export (sysref),
.rx_ref_clk_clk (ref_clk1),
.rx_sync_export (rx_sync),
.rx_sysref_export (sysref),
.sys_clk_clk (sys_clk),
.sys_ddr_mem_mem_ck (sys_ddr_clk_p),
.sys_ddr_mem_mem_ck_n (sys_ddr_clk_n),
.sys_ddr_mem_mem_a (sys_ddr_a),
.sys_ddr_mem_mem_act_n (sys_ddr_act_n),
.sys_ddr_mem_mem_ba (sys_ddr_ba),
.sys_ddr_mem_mem_bg (sys_ddr_bg),
.sys_ddr_mem_mem_cke (sys_ddr_cke),
.sys_ddr_mem_mem_cs_n (sys_ddr_cs_n),
.sys_ddr_mem_mem_odt (sys_ddr_odt),
.sys_ddr_mem_mem_reset_n (sys_ddr_reset_n),
.sys_ddr_mem_mem_par (sys_ddr_par),
.sys_ddr_mem_mem_alert_n (sys_ddr_alert_n),
.sys_ddr_mem_mem_dqs (sys_ddr_dqs_p),
.sys_ddr_mem_mem_dqs_n (sys_ddr_dqs_n),
.sys_ddr_mem_mem_dq (sys_ddr_dq),
.sys_ddr_mem_mem_dbi_n (sys_ddr_dbi_n),
.sys_ddr_oct_oct_rzqin (sys_ddr_rzq),
.sys_ddr_ref_clk_clk (sys_ddr_ref_clk),
.sys_ddr_status_local_cal_success (sys_ddr_cal_success),
.sys_ddr_status_local_cal_fail (sys_ddr_cal_fail),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
.sys_hps_ddr_mem_a (hps_ddr_a),
.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
.sys_hps_ddr_mem_ba (hps_ddr_ba),
.sys_hps_ddr_mem_bg (hps_ddr_bg),
.sys_hps_ddr_mem_cke (hps_ddr_cke),
.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
.sys_hps_ddr_mem_odt (hps_ddr_odt),
.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
.sys_hps_ddr_mem_par (hps_ddr_par),
.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
.sys_hps_ddr_mem_dq (hps_ddr_dq),
.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
.sys_hps_ddr_rstn_reset_n (sys_resetn),
.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
.sys_hps_out_rstn_reset_n (sys_hps_resetn),
.sys_hps_rstn_reset_n (sys_resetn),
.sys_rstn_reset_n (sys_resetn_s),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn_s),
.tx_data_0_tx_serial_data (tx_data[0]),
.tx_data_1_tx_serial_data (tx_data[1]),
.tx_data_2_tx_serial_data (tx_data[2]),
.tx_data_3_tx_serial_data (tx_data[3]),
.tx_fifo_bypass_bypass (dac_fifo_bypass),
.tx_ref_clk_clk (ref_clk1),
.tx_sync_export (tx_sync),
.tx_sysref_export (sysref));
endmodule
// ***************************************************************************
// ***************************************************************************