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daq1_cpld: Do not forward the first eight clock cycles of fmc_spi_sclk to sclk

main
Istvan Csomortani 2016-02-15 19:26:58 +02:00
parent 9370246cfa
commit 051ac307e6
1 changed files with 3 additions and 3 deletions
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6
projects/daq1/cpld/daq1_cpld.v
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@ -119,7 +119,7 @@ module daq1_cpld (
localparam [ 6:0] DAC_STATUS_ADDR = 7'h21; localparam [ 6:0] DAC_STATUS_ADDR = 7'h21;
localparam [ 6:0] CLK_STATUS_ADDR = 7'h22; localparam [ 6:0] CLK_STATUS_ADDR = 7'h22;
localparam [ 7:0] CPLD_VERSION = 8'hDAC10101; localparam [ 7:0] CPLD_VERSION = 8'h0101;
// Internal Registers/Signals // Internal Registers/Signals
@ -172,13 +172,13 @@ module daq1_cpld (
// SPI control and data // SPI control and data
assign sclk = fmc_spi_sclk;
assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ; assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ;
assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s; assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s;
assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit; assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
assign rdnwr = ~fmc_cpld_addr[7]; assign rdnwr = ~fmc_cpld_addr[7];
assign sclk = (~(fmc_spi_csn | fmc_spi_csn_enb)) ? fmc_spi_sclk : 1'b0;
always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
if (fmc_spi_csn == 1'b1) begin if (fmc_spi_csn == 1'b1) begin
fmc_spi_counter <= 6'h0; fmc_spi_counter <= 6'h0;