diff --git a/library/altera/avl_dacfifo/util_dacfifo_bypass.v b/library/altera/avl_dacfifo/util_dacfifo_bypass.v
index 48fc5e73e..dadff99f9 100644
--- a/library/altera/avl_dacfifo/util_dacfifo_bypass.v
+++ b/library/altera/avl_dacfifo/util_dacfifo_bypass.v
@@ -104,41 +104,10 @@ module util_dacfifo_bypass #(
   wire    [DMA_ADDRESS_WIDTH:0]         dma_address_diff_s;
   wire    [DAC_ADDRESS_WIDTH:0]         dac_address_diff_s;
 
-  // binary to grey conversion
-
-  function [7:0] b2g;
-    input [7:0] b;
-    reg   [7:0] g;
-    begin
-      g[7] = b[7];
-      g[6] = b[7] ^ b[6];
-      g[5] = b[6] ^ b[5];
-      g[4] = b[5] ^ b[4];
-      g[3] = b[4] ^ b[3];
-      g[2] = b[3] ^ b[2];
-      g[1] = b[2] ^ b[1];
-      g[0] = b[1] ^ b[0];
-      b2g = g;
-    end
-  endfunction
-
-  // grey to binary conversion
-
-  function [7:0] g2b;
-    input [7:0] g;
-    reg   [7:0] b;
-    begin
-      b[7] = g[7];
-      b[6] = b[7] ^ g[6];
-      b[5] = b[6] ^ g[5];
-      b[4] = b[5] ^ g[4];
-      b[3] = b[4] ^ g[3];
-      b[2] = b[3] ^ g[2];
-      b[1] = b[2] ^ g[1];
-      b[0] = b[1] ^ g[0];
-      g2b = b;
-    end
-  endfunction
+  wire    [(DMA_ADDRESS_WIDTH-1):0]     dma_mem_waddr_b2g_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]     dac_mem_raddr_b2g_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m2_g2b_s;
+  wire    [(DMA_ADDRESS_WIDTH-1):0]     dac_mem_waddr_m2_g2b_s;
 
   // An asymmetric memory to transfer data from DMAC interface to DAC interface
 
@@ -170,10 +139,16 @@ module util_dacfifo_bypass #(
       if (dma_mem_wea_s == 1'b1) begin
         dma_mem_waddr <= dma_mem_waddr + 1'b1;
       end
-      dma_mem_waddr_g <= b2g(dma_mem_waddr);
+      dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
     end
   end
 
+  ad_b2g #(
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
+  i_dma_mem_waddr_b2g (
+    .din (dma_mem_waddr),
+    .dout (dma_mem_waddr_b2g_s));
+
   // The memory module request data until reaches the high threshold.
 
   always @(posedge dma_clk) begin
@@ -186,7 +161,7 @@ module util_dacfifo_bypass #(
     end else begin
       dma_mem_raddr_m1 <= dac_mem_raddr_g;
       dma_mem_raddr_m2 <= dma_mem_raddr_m1;
-      dma_mem_raddr <= g2b(dma_mem_raddr_m2);
+      dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
       dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
       if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
         dma_ready_out <= 1'b0;
@@ -196,6 +171,12 @@ module util_dacfifo_bypass #(
     end
   end
 
+  ad_g2b #(
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
+  i_dma_mem_raddr_g2b (
+    .din (dma_mem_raddr_m2),
+    .dout (dma_mem_raddr_m2_g2b_s));
+
   // relative address offset on dma domain
   assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
   assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
@@ -229,10 +210,16 @@ module util_dacfifo_bypass #(
       if (dac_mem_rea_s == 1'b1) begin
         dac_mem_raddr <= dac_mem_raddr + 1'b1;
       end
-      dac_mem_raddr_g <= b2g(dac_mem_raddr);
+      dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
     end
   end
 
+  ad_b2g #(
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
+  i_dac_mem_raddr_b2g (
+    .din (dac_mem_raddr),
+    .dout (dac_mem_raddr_b2g_s));
+
   // The memory module is ready if it's not empty
 
   always @(posedge dac_clk) begin
@@ -245,7 +232,7 @@ module util_dacfifo_bypass #(
     end else begin
       dac_mem_waddr_m1 <= dma_mem_waddr_g;
       dac_mem_waddr_m2 <= dac_mem_waddr_m1;
-      dac_mem_waddr <= g2b(dac_mem_waddr_m2);
+      dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
       dac_mem_addr_diff <= dac_address_diff_s[DAC_ADDRESS_WIDTH-1:0];
       if (dac_mem_addr_diff > 0) begin
         dac_mem_ready <= 1'b1;
@@ -255,6 +242,12 @@ module util_dacfifo_bypass #(
     end
   end
 
+  ad_g2b #(
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
+  i_dac_mem_waddr_g2b (
+    .din (dac_mem_waddr_m2),
+    .dout (dac_mem_waddr_m2_g2b_s));
+
   // define underflow
 
   always @(posedge dac_clk) begin
diff --git a/library/xilinx/axi_dacfifo/util_dacfifo_bypass.v b/library/xilinx/axi_dacfifo/util_dacfifo_bypass.v
index bedf17542..5865ba18a 100644
--- a/library/xilinx/axi_dacfifo/util_dacfifo_bypass.v
+++ b/library/xilinx/axi_dacfifo/util_dacfifo_bypass.v
@@ -104,41 +104,10 @@ module util_dacfifo_bypass #(
   wire    [DMA_ADDRESS_WIDTH:0]         dma_address_diff_s;
   wire    [DAC_ADDRESS_WIDTH:0]         dac_address_diff_s;
 
-  // binary to grey conversion
-
-  function [7:0] b2g;
-    input [7:0] b;
-    reg   [7:0] g;
-    begin
-      g[7] = b[7];
-      g[6] = b[7] ^ b[6];
-      g[5] = b[6] ^ b[5];
-      g[4] = b[5] ^ b[4];
-      g[3] = b[4] ^ b[3];
-      g[2] = b[3] ^ b[2];
-      g[1] = b[2] ^ b[1];
-      g[0] = b[1] ^ b[0];
-      b2g = g;
-    end
-  endfunction
-
-  // grey to binary conversion
-
-  function [7:0] g2b;
-    input [7:0] g;
-    reg   [7:0] b;
-    begin
-      b[7] = g[7];
-      b[6] = b[7] ^ g[6];
-      b[5] = b[6] ^ g[5];
-      b[4] = b[5] ^ g[4];
-      b[3] = b[4] ^ g[3];
-      b[2] = b[3] ^ g[2];
-      b[1] = b[2] ^ g[1];
-      b[0] = b[1] ^ g[0];
-      g2b = b;
-    end
-  endfunction
+  wire    [(DMA_ADDRESS_WIDTH-1):0]     dma_mem_waddr_b2g_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]     dac_mem_raddr_b2g_s;
+  wire    [(DAC_ADDRESS_WIDTH-1):0]     dma_mem_raddr_m2_g2b_s;
+  wire    [(DMA_ADDRESS_WIDTH-1):0]     dac_mem_waddr_m2_g2b_s;
 
   // An asymmetric memory to transfer data from DMAC interface to DAC interface
 
@@ -173,12 +142,18 @@ module util_dacfifo_bypass #(
       dma_mem_waddr_g <= 'h0;
     end else begin
       if (dma_mem_wea_s == 1'b1) begin
-        dma_mem_waddr <= dma_mem_waddr + 1;
+        dma_mem_waddr <= dma_mem_waddr + 1'b1;
       end
-      dma_mem_waddr_g <= b2g(dma_mem_waddr);
+      dma_mem_waddr_g <= dma_mem_waddr_b2g_s;
     end
   end
 
+  ad_b2g #(
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
+  i_dma_mem_waddr_b2g (
+    .din (dma_mem_waddr),
+    .dout (dma_mem_waddr_b2g_s));
+
   // The memory module request data until reaches the high threshold.
 
   always @(posedge dma_clk) begin
@@ -191,7 +166,7 @@ module util_dacfifo_bypass #(
     end else begin
       dma_mem_raddr_m1 <= dac_mem_raddr_g;
       dma_mem_raddr_m2 <= dma_mem_raddr_m1;
-      dma_mem_raddr <= g2b(dma_mem_raddr_m2);
+      dma_mem_raddr <= dma_mem_raddr_m2_g2b_s;
       dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
       if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
         dma_ready_out <= 1'b0;
@@ -201,6 +176,12 @@ module util_dacfifo_bypass #(
     end
   end
 
+  ad_g2b #(
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
+  i_dma_mem_raddr_g2b (
+    .din (dma_mem_raddr_m2),
+    .dout (dma_mem_raddr_m2_g2b_s));
+
   // relative address offset on dma domain
   assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
   assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
@@ -234,10 +215,16 @@ module util_dacfifo_bypass #(
       if (dac_mem_rea_s == 1'b1) begin
         dac_mem_raddr <= dac_mem_raddr + 1;
       end
-      dac_mem_raddr_g <= b2g(dac_mem_raddr);
+      dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
     end
   end
 
+  ad_b2g #(
+    .DATA_WIDTH (DAC_ADDRESS_WIDTH))
+  i_dac_mem_raddr_b2g (
+    .din (dac_mem_raddr),
+    .dout (dac_mem_raddr_b2g_s));
+
   // The memory module is ready if it's not empty
 
   always @(posedge dac_clk) begin
@@ -250,7 +237,7 @@ module util_dacfifo_bypass #(
     end else begin
       dac_mem_waddr_m1 <= dma_mem_waddr_g;
       dac_mem_waddr_m2 <= dac_mem_waddr_m1;
-      dac_mem_waddr <= g2b(dac_mem_waddr_m2);
+      dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
       dac_mem_addr_diff <= dac_address_diff_s[DAC_ADDRESS_WIDTH-1:0];
       if (dac_mem_addr_diff > 0) begin
         dac_mem_ready <= 1'b1;
@@ -260,6 +247,12 @@ module util_dacfifo_bypass #(
     end
   end
 
+  ad_g2b #(
+    .DATA_WIDTH (DMA_ADDRESS_WIDTH))
+  i_dac_mem_waddr_g2b (
+    .din (dac_mem_waddr_m2),
+    .dout (dac_mem_waddr_m2_g2b_s));
+
   // define underflow
 
   always @(posedge dac_clk) begin