From 04ce10a570dc6bff74620da68e216d7b92780907 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Tue, 14 Aug 2018 13:48:32 +0100 Subject: [PATCH] cosmetics: Change Altera to Intel in comments --- library/axi_ad9361/intel/axi_ad9361_cmos_if.v | 2 +- library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 2 +- library/axi_dmac/axi_dmac_hw.tcl | 2 +- library/axi_dmac/axi_dmac_ip.tcl | 4 ++-- library/intel/axi_adxcvr/axi_adxcvr_up.v | 2 +- library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v | 2 +- library/xilinx/axi_adxcvr/axi_adxcvr_up.v | 2 -- projects/adrv9371x/a10gx/system_top.v | 2 +- projects/daq2/a10gx/system_top.v | 2 +- projects/daq3/a10gx/system_top.v | 2 +- 10 files changed, 10 insertions(+), 12 deletions(-) diff --git a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v index 9e3f16d88..4b650345b 100644 --- a/library/axi_ad9361/intel/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/intel/axi_ad9361_cmos_if.v @@ -116,7 +116,7 @@ module axi_ad9361_cmos_if #( output up_drp_ready, output up_drp_locked); - // cmos is not supported on altera platforms yet. + // cmos is not supported on intel platforms yet. assign tx_clk_out = 1'd0; assign tx_frame_out = 1'd0; diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index 96a31c052..4e2998b1e 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -206,7 +206,7 @@ module axi_ad9361_lvds_if #( rx_locked <= rx_locked_m1; end - // altera-equivalence + // intel-equivalence always @(posedge l_clk) begin rx_valid <= ~rx_valid; diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl index f074cf34b..047b8de6d 100644 --- a/library/axi_dmac/axi_dmac_hw.tcl +++ b/library/axi_dmac/axi_dmac_hw.tcl @@ -370,7 +370,7 @@ proc add_axi_master_interface {axi_type port suffix} { add_interface_port $port ${port}_arburst arburst Output 2 add_interface_port $port ${port}_arcache arcache Output 4 add_interface_port $port ${port}_arprot arprot Output 3 - # Some signals are mandatory in Altera's implementation of AXI3 + # Some signals are mandatory in Intel's implementation of AXI3 # awid, awlock, wid, bid, arid, arlock, rid, rlast # Hide them in AXI4 add_interface_port $port ${port}_awid awid Output 1 diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index b00e174ed..58074e8f1 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -83,7 +83,7 @@ adi_set_ports_dependency "fifo_rd" \ adi_set_ports_dependency "dest_diag_level_bursts" \ "(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)" -# These are in the design to keep the Altera tools happy which can't handle +# These are in the design to keep the Intel tools happy which can't handle # uni-directional AXI interfaces. The Xilinx tools can and do a better job when # they know that the interface is uni-directional, so disable the ports. set dummy_axi_ports [list \ @@ -119,7 +119,7 @@ set dummy_axi_ports [list \ "m_src_axi_bresp" \ ] -# These are in the design to keep the Altera tools happy which require +# These are in the design to keep the Intel tools happy which require # certain signals in AXI3 mode even if these are defined as optinal in the standard. lappend dummy_axi_ports \ "m_dest_axi_awid" \ diff --git a/library/intel/axi_adxcvr/axi_adxcvr_up.v b/library/intel/axi_adxcvr/axi_adxcvr_up.v index 6e43bfe7a..847bf6ce6 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_up.v +++ b/library/intel/axi_adxcvr/axi_adxcvr_up.v @@ -140,7 +140,7 @@ module axi_adxcvr_up #( end end - // Specific to Altera + // Specific to Intel assign up_rparam_s[31:28] = 8'd0; assign up_rparam_s[27:24] = XCVR_TYPE[3:0]; diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v index ded0bf4f0..c06f0026d 100644 --- a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v +++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v @@ -97,7 +97,7 @@ end * Shift register with variable tap for accessing the stored data. * * This has slightly better utilization on Xilinx based platforms than the dual - * port RAM approach, but there is no equivalent primitive on Altera resulting + * port RAM approach, but there is no equivalent primitive on Intel resulting * in increased utilization since it needs to be implemented used registers and * muxes. * diff --git a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v index 6a9fcb915..5f44d3253 100644 --- a/library/xilinx/axi_adxcvr/axi_adxcvr_up.v +++ b/library/xilinx/axi_adxcvr/axi_adxcvr_up.v @@ -478,8 +478,6 @@ module axi_adxcvr_up #( assign up_rack = up_rreq_d; assign up_rdata = up_rdata_d; - // altera specific - assign up_rparam_s[31:24] = 8'd0; // xilinx specific diff --git a/projects/adrv9371x/a10gx/system_top.v b/projects/adrv9371x/a10gx/system_top.v index d4bb1d4a7..9fd20fd2f 100644 --- a/projects/adrv9371x/a10gx/system_top.v +++ b/projects/adrv9371x/a10gx/system_top.v @@ -169,7 +169,7 @@ module system_top ( assign gpio_bd_o = gpio_o[15:0]; - // User code space at offset 0x0930_0000 per Altera's Board Update Portal + // User code space at offset 0x0930_0000 per Intel's Board Update Portal // reference design used to program flash assign flash_addr = flash_addr_raw + 28'h9300000; diff --git a/projects/daq2/a10gx/system_top.v b/projects/daq2/a10gx/system_top.v index a117eb016..fe0a9e5c4 100644 --- a/projects/daq2/a10gx/system_top.v +++ b/projects/daq2/a10gx/system_top.v @@ -133,7 +133,7 @@ module system_top ( wire [ 7:0] spi_csn_s; wire dac_fifo_bypass; - // User code space at offset 0x0930_0000 per Altera's Board Update Portal + // User code space at offset 0x0930_0000 per Intel's Board Update Portal // reference design used to program flash wire [23:0] flash_addr_raw; diff --git a/projects/daq3/a10gx/system_top.v b/projects/daq3/a10gx/system_top.v index e32d8829b..9a800a80e 100644 --- a/projects/daq3/a10gx/system_top.v +++ b/projects/daq3/a10gx/system_top.v @@ -177,7 +177,7 @@ module system_top ( assign gpio_bd_o = gpio_o[15:0]; - // User code space at offset 0x0930_0000 per Altera's Board Update Portal + // User code space at offset 0x0930_0000 per Intel's Board Update Portal // reference design used to program flash assign flash_addr = flash_addr_raw + 28'h9300000;