diff --git a/library/axi_ad9434/axi_ad9434_constr.xdc b/library/axi_ad9434/axi_ad9434_constr.xdc
index 7e6bc712b..8b1378917 100644
--- a/library/axi_ad9434/axi_ad9434_constr.xdc
+++ b/library/axi_ad9434/axi_ad9434_constr.xdc
@@ -1,44 +1 @@
-set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
-set ad9434_clk [get_clocks -of_objects [get_ports adc_clk]]
 
-set_property ASYNC_REG TRUE \
-  [get_cells -hier *toggle_m1_reg*] \
-  [get_cells -hier *toggle_m2_reg*] \
-  [get_cells -hier *state_m1_reg*] \
-  [get_cells -hier *state_m2_reg*]
-
-set_false_path \
-  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay -datapath_only \
-  -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $ad9434_clk]
-
-set_false_path \
-  -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay -datapath_only \
-  -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $up_clk]
-
-set_false_path \
-  -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_false_path \
-  -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
-set_max_delay -datapath_only \
-  -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-  -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
-  [get_property PERIOD $up_clk]
-
-set_false_path \
-  -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
diff --git a/library/axi_ad9434/axi_ad9434_ip.tcl b/library/axi_ad9434/axi_ad9434_ip.tcl
index 22ab4979f..d13a1bbd6 100644
--- a/library/axi_ad9434/axi_ad9434_ip.tcl
+++ b/library/axi_ad9434/axi_ad9434_ip.tcl
@@ -18,6 +18,7 @@ adi_ip_files axi_ad9434 [list \
   "$ad_hdl_dir/library/common/up_adc_channel.v" \
   "$ad_hdl_dir/library/common/ad_pnmon.v" \
   "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
   "axi_ad9434_if.v" \
   "axi_ad9434_pnmon.v" \
   "axi_ad9434_core.v" \
@@ -27,7 +28,8 @@ adi_ip_files axi_ad9434 [list \
 adi_ip_properties axi_ad9434
 
 adi_ip_constraints axi_ad9434 [list \
-  "axi_ad9434_constr.xdc" ]
+  "axi_ad9434_constr.xdc" \
+  "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc"]
 
 set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]