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axi_spi_engine: Add pulse_width to the CNV configuration interface 

The conversion start configuration interface can be used to configure
a PWM generator (util_pulse_gen) to generate CNV for a precission ADC.
main
Istvan Csomortani 2020-05-15 17:51:17 +03:00 committed by István Csomortáni
parent 2506239a8a
commit 0402ce85e4
1 changed files with 8 additions and 4 deletions
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12
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -122,14 +122,15 @@ module axi_spi_engine #(
output offload0_mem_reset, output offload0_mem_reset,
output offload0_enable, output offload0_enable,
input offload0_enabled, input offload0_enabled,
output offload_sync_ready, output offload_sync_ready,
input offload_sync_valid, input offload_sync_valid,
input [7:0] offload_sync_data, input [7:0] offload_sync_data,
// PWM control for internal triggering // Configuration interface conversion start generator (PWM)
output reg [31:0] pulse_gen_period, output reg [31:0] pulse_gen_period,
output reg [31:0] pulse_gen_width,
output reg pulse_gen_load); output reg pulse_gen_load);
localparam PCORE_VERSION = 'h010071; localparam PCORE_VERSION = 'h010071;
@ -311,7 +312,8 @@ module axi_spi_engine #(
up_irq_mask <= 'h00; up_irq_mask <= 'h00;
offload0_enable_reg <= 1'b0; offload0_enable_reg <= 1'b0;
offload0_mem_reset_reg <= 1'b0; offload0_mem_reset_reg <= 1'b0;
pulse_gen_period <= 'h00; pulse_gen_period <= 32'h0;
pulse_gen_width <= 32'h0;
end else begin end else begin
if (up_wreq_s) begin if (up_wreq_s) begin
case (up_waddr_s) case (up_waddr_s)
@ -319,6 +321,7 @@ module axi_spi_engine #(
8'h40: offload0_enable_reg <= up_wdata_s[0]; 8'h40: offload0_enable_reg <= up_wdata_s[0];
8'h42: offload0_mem_reset_reg <= up_wdata_s[0]; 8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
8'h48: pulse_gen_period <= up_wdata_s; 8'h48: pulse_gen_period <= up_wdata_s;
8'h49: pulse_gen_width <= up_wdata_s;
endcase endcase
end end
end end
@ -353,6 +356,7 @@ module axi_spi_engine #(
8'h40: up_rdata_ff <= {offload0_enable_reg}; 8'h40: up_rdata_ff <= {offload0_enable_reg};
8'h41: up_rdata_ff <= {offload0_enabled_s}; 8'h41: up_rdata_ff <= {offload0_enabled_s};
8'h48: up_rdata_ff <= pulse_gen_period; 8'h48: up_rdata_ff <= pulse_gen_period;
8'h49: up_rdata_ff <= pulse_gen_width;
default: up_rdata_ff <= 'h00; default: up_rdata_ff <= 'h00;
endcase endcase
end end