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daq1_zed: Lower the adc and daq clock to 450MHz 

The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
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AndreiGrozav 2017-09-26 10:33:35 +03:00
parent 7a3c4ab81f
commit 03e744f0f1
1 changed files with 2 additions and 2 deletions
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projects/daq1/zed/system_constr.xdc
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@ -78,6 +78,6 @@ set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports spi_int]
# clocks
create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 2.00 [get_ports adc_clk_in_p]
create_clock -name dac_clk_in -period 2.222 [get_ports dac_clk_in_p]
create_clock -name adc_clk_in -period 2.222 [get_ports adc_clk_in_p]