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axi_ad9671: Fixed synchronization mechanism

main
Adrian Costina 2015-10-09 13:15:12 +03:00
parent 8321d5a4fb
commit 03b225a802
1 changed files with 2 additions and 2 deletions
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4
library/axi_ad9671/axi_ad9671_if.v
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@ -201,12 +201,12 @@ module axi_ad9671_if (
adc_raddr_out <= 4'h8; adc_raddr_out <= 4'h8;
adc_sync_status <= 1'b0; adc_sync_status <= 1'b0;
end else begin end else begin
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_sync_status <= 1'b0; adc_sync_status <= 1'b0;
end else if(adc_sync_s == 1'b1) begin end else if(adc_sync_s == 1'b1) begin
adc_sync_status <= 1'b1; adc_sync_status <= 1'b1;
end end
if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
adc_waddr <= 4'h0; adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8; adc_raddr_out <= 4'h8;
end else if (int_valid == 1'b1) begin end else if (int_valid == 1'b1) begin