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fmcadc5- syntax/port name fixes

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Rejeesh Kutty 2017-05-10 16:30:15 -04:00
parent fea6eb68be
commit 039ae9ae92
5 changed files with 15 additions and 16 deletions
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1
library/axi_ad9625/axi_ad9625.v
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@ -198,7 +198,6 @@ module axi_ad9625 #(
.adc_clk_ratio (32'd16), .adc_clk_ratio (32'd16),
.adc_start_code (), .adc_start_code (),
.adc_sync (), .adc_sync (),
.adc_sref_sync (),
.adc_sref_sync (adc_sref_sync_s), .adc_sref_sync (adc_sref_sync_s),
.up_status_pn_err (up_adc_pn_err_s), .up_status_pn_err (up_adc_pn_err_s),
.up_status_pn_oos (up_adc_pn_oos_s), .up_status_pn_oos (up_adc_pn_oos_s),

8
library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
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@ -58,8 +58,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
input [255:0] rx_data_0, input [255:0] rx_data_0,
input rx_enable_1, input rx_enable_1,
input [255:0] rx_data_1, input [255:0] rx_data_1,
output rx_cor_enable, output rx_enable,
output [511:0] rx_cor_data, output [511:0] rx_data,
// calibration signal // calibration signal
@ -644,8 +644,8 @@ module axi_fmcadc5_sync #(parameter integer ID = 0) (
.rx_data_0 (rx_data_0), .rx_data_0 (rx_data_0),
.rx_enable_1 (rx_enable_1), .rx_enable_1 (rx_enable_1),
.rx_data_1 (rx_data_1), .rx_data_1 (rx_data_1),
.rx_cor_enable (rx_cor_enable), .rx_enable (rx_enable),
.rx_cor_data (rx_cor_data), .rx_data (rx_data),
.rx_cal_enable (rx_cal_enable), .rx_cal_enable (rx_cal_enable),
.rx_cal_done_t (rx_cal_done_t_s), .rx_cal_done_t (rx_cal_done_t_s),
.rx_cal_max_0 (rx_cal_max_0_s), .rx_cal_max_0 (rx_cal_max_0_s),

14
library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
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@ -49,8 +49,8 @@ module axi_fmcadc5_sync_calcor (
input [255:0] rx_data_0, input [255:0] rx_data_0,
input rx_enable_1, input rx_enable_1,
input [255:0] rx_data_1, input [255:0] rx_data_1,
output rx_cor_enable, output rx_enable,
output [511:0] rx_cor_data, output [511:0] rx_data,
// calibration signals // calibration signals
@ -67,7 +67,7 @@ module axi_fmcadc5_sync_calcor (
// internal registers // internal registers
reg rx_cor_enable_int = 'd0; reg rx_enable_int = 'd0;
reg [ 15:0] rx_cor_data_0[0:15]; reg [ 15:0] rx_cor_data_0[0:15];
reg [ 15:0] rx_cor_data_1[0:15]; reg [ 15:0] rx_cor_data_1[0:15];
reg rx_cal_done_int_t = 'd0; reg rx_cal_done_int_t = 'd0;
@ -109,16 +109,16 @@ module axi_fmcadc5_sync_calcor (
// offset & gain // offset & gain
assign rx_cor_enable = rx_cor_enable_int; assign rx_enable = rx_enable_int;
always @(posedge rx_clk) begin always @(posedge rx_clk) begin
rx_cor_enable_int = rx_enable_0 & rx_enable_1; rx_enable_int = rx_enable_0 & rx_enable_1;
end end
generate generate
for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data
assign rx_cor_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15]; assign rx_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15];
assign rx_cor_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15]; assign rx_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15];
end end
endgenerate endgenerate

4
projects/fmcadc5/common/fmcadc5_bd.tcl
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@ -172,8 +172,8 @@ ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_sync/rx_enable_0
ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_sync/rx_data_0 ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_sync/rx_data_0
ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_sync/rx_enable_1 ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_sync/rx_enable_1
ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_sync/rx_data_1 ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_sync/rx_data_1
ad_connect axi_fmcadc5_sync/rx_cor_enable axi_ad9625_fifo/adc_wr ad_connect axi_fmcadc5_sync/rx_enable axi_ad9625_fifo/adc_wr
ad_connect axi_fmcadc5_sync/rx_cor_data axi_ad9625_fifo/adc_wdata ad_connect axi_fmcadc5_sync/rx_data axi_ad9625_fifo/adc_wdata
ad_connect axi_fmcadc5_sync/rx_sysref axi_ad9625_0_jesd/rx_sysref ad_connect axi_fmcadc5_sync/rx_sysref axi_ad9625_0_jesd/rx_sysref
ad_connect axi_ad9625_0_jesd/rx_sync axi_fmcadc5_sync/rx_sync_0 ad_connect axi_ad9625_0_jesd/rx_sync axi_fmcadc5_sync/rx_sync_0
ad_connect axi_fmcadc5_sync/rx_sysref axi_ad9625_1_jesd/rx_sysref ad_connect axi_fmcadc5_sync/rx_sysref axi_ad9625_1_jesd/rx_sysref

4
projects/fmcadc5/vc707/system_bd.tcl
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@ -25,8 +25,8 @@ ad_ip_parameter ila_adc CONFIG.C_PROBE1_WIDTH 16
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/din_clk
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/din_rst
ad_connect axi_fmcadc5_sync/rx_cor_enable mfifo_adc/din_valid ad_connect axi_fmcadc5_sync/rx_enable mfifo_adc/din_valid
ad_connect axi_fmcadc5_sync/rx_cor_data mfifo_adc/din_data_0 ad_connect axi_fmcadc5_sync/rx_data mfifo_adc/din_data_0
ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst ad_connect axi_ad9625_0_jesd_rstgen/peripheral_reset mfifo_adc/dout_rst
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 mfifo_adc/dout_clk
ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 ila_adc/clk