diff --git a/projects/adrv9001/zcu102/lvds_constr.xdc b/projects/adrv9001/zcu102/lvds_constr.xdc
index 27c744e8c..739f1eb7b 100644
--- a/projects/adrv9001/zcu102/lvds_constr.xdc
+++ b/projects/adrv9001/zcu102/lvds_constr.xdc
@@ -47,9 +47,20 @@ create_clock -name rx2_dclk_out   -period  2.034 [get_ports rx2_dclk_in_p]
 create_clock -name tx1_dclk_out   -period  2.034 [get_ports tx1_dclk_in_p]
 create_clock -name tx2_dclk_out   -period  2.034 [get_ports tx2_dclk_in_p]
 
-# Allow max skew of 0.5 ns between input clocks
-set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out]
-set_clock_latency -source -early -0.25 [get_clocks rx2_dclk_out]
+# Allow max skew of 0.25 ns between input clocks
+set_clock_latency -source -early -0.125 [get_clocks rx1_dclk_out]
+set_clock_latency -source -early -0.125 [get_clocks rx2_dclk_out]
+
+set_clock_latency -source -late 0.125 [get_clocks rx1_dclk_out]
+set_clock_latency -source -late 0.125 [get_clocks rx2_dclk_out]
+
+set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_1 \
+  [list [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_div_clk_buf/O]] \
+        [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_1_phy/i_clk_buf_fast/O]] \
+  ]
+
+set_property CLOCK_DELAY_GROUP BALANCE_CLOCKS_2 \
+  [list [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_div_clk_buf/O]] \
+        [get_nets -of [get_pins i_system_wrapper/system_i/axi_adrv9001/inst/i_if/i_rx_2_phy/i_clk_buf_fast/O]] \
+  ]
 
-set_clock_latency -source -late 0.25 [get_clocks rx1_dclk_out]
-set_clock_latency -source -late 0.25 [get_clocks rx2_dclk_out]