From 034aa7c1ee2b2e3d6968339d341758e83800573c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 8 Jun 2017 10:50:37 -0400 Subject: [PATCH] altera 16.1- recommends using fpll for dedicated low skew clock routing --- library/altera/avl_adxcvr/avl_adxcvr_hw.tcl | 35 ++++++++++++--------- library/altera/axi_adxcvr/axi_adxcvr_hw.tcl | 2 +- 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl index 9812d3d9f..9de1eddb5 100755 --- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl @@ -143,27 +143,32 @@ proc p_avl_adxcvr {} { add_interface core_pll_locked conduit end set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked + add_instance alt_core_pll_reconfig altera_pll_reconfig + add_connection alt_sys_clk.clk_reset alt_core_pll_reconfig.mgmt_reset + add_connection alt_sys_clk.clk alt_core_pll_reconfig.mgmt_clk + add_connection alt_core_pll_reconfig.reconfig_to_pll alt_core_pll.reconfig_to_pll + add_connection alt_core_pll.reconfig_from_pll alt_core_pll_reconfig.reconfig_from_pll + add_interface core_pll_reconfig avalon slave + set_interface_property core_pll_reconfig EXPORT_OF alt_core_pll_reconfig.mgmt_avalon_slave + } else { - add_instance alt_core_pll altera_iopll - set_instance_parameter_value alt_core_pll {gui_en_reconf} {1} + add_instance alt_core_pll altera_xcvr_fpll_a10 + set_instance_parameter_value alt_core_pll {gui_fpll_mode} {0} set_instance_parameter_value alt_core_pll {gui_reference_clock_frequency} $m_refclk_frequency - set_instance_parameter_value alt_core_pll {gui_use_locked} {1} - set_instance_parameter_value alt_core_pll {gui_output_clock_frequency0} $m_coreclk_frequency - add_connection alt_ref_clk.out_clk alt_core_pll.refclk - add_connection alt_sys_clk.clk_reset alt_core_pll.reset + set_instance_parameter_value alt_core_pll {gui_desired_outclk0_frequency} $m_coreclk_frequency + set_instance_parameter_value alt_core_pll {enable_pll_reconfig} {1} + set_instance_parameter_value alt_core_pll {set_capability_reg_enable} {1} + set_instance_parameter_value alt_core_pll {set_csr_soft_logic_enable} {1} + add_connection alt_ref_clk.out_clk alt_core_pll.pll_refclk0 add_interface core_pll_locked conduit end - set_interface_property core_pll_locked EXPORT_OF alt_core_pll.locked + set_interface_property core_pll_locked EXPORT_OF alt_core_pll.pll_locked + add_connection alt_sys_clk.clk_reset alt_core_pll.reconfig_reset0 + add_connection alt_sys_clk.clk alt_core_pll.reconfig_clk0 + add_interface core_pll_reconfig avalon slave + set_interface_property core_pll_reconfig EXPORT_OF alt_core_pll.reconfig_avmm0 } - add_instance alt_core_pll_reconfig altera_pll_reconfig - add_connection alt_sys_clk.clk_reset alt_core_pll_reconfig.mgmt_reset - add_connection alt_sys_clk.clk alt_core_pll_reconfig.mgmt_clk - add_connection alt_core_pll_reconfig.reconfig_to_pll alt_core_pll.reconfig_to_pll - add_connection alt_core_pll.reconfig_from_pll alt_core_pll_reconfig.reconfig_from_pll - add_interface core_pll_reconfig avalon slave - set_interface_property core_pll_reconfig EXPORT_OF alt_core_pll_reconfig.mgmt_avalon_slave - add_instance alt_core_clk altera_clock_bridge set_instance_parameter_value alt_core_clk {EXPLICIT_CLOCK_RATE} $m_coreclk_frequency add_connection alt_core_pll.outclk0 alt_core_clk.in_clk diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl index a2a83857c..db765cb12 100644 --- a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl +++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl @@ -77,7 +77,7 @@ ad_alt_intf reset up_rst output 1 s_axi_clock set_interface_property if_up_rst associatedResetSinks s_axi_reset add_interface core_pll_locked conduit end -add_interface_port core_pll_locked up_pll_locked export Input 1 +add_interface_port core_pll_locked up_pll_locked pll_locked Input 1 # name changes