jesd204: create wrappers around TPLs in BD
Laszlo Nagy
Laszlo Nagy
parent
d8e11cfce5
commit
032bf7c3ef
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@ -195,3 +195,223 @@ proc adi_axi_jesd204_rx_create {ip_name num_lanes {num_links 1}} {
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return -options $resultoptions $resulttext
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}
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# L M S N & NP
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proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width} {
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set link_layer_bytes_per_beat 4
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if {$num_of_lanes < 1 || $num_of_lanes > 8} {
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return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-8)"
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}
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# F = (M * N * S) / (L * 8)
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set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)];
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# one beat per lane must accommodate at least one frame
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set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)]
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# datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N)
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set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)];
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startgroup
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set result [catch {
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create_bd_cell -type hier $ip_name
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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# Interface to link layer
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create_bd_pin -dir I -type clk "${ip_name}/link_clk"
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link"
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# Interface to application layer
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create_bd_pin -dir I "${ip_name}/dac_dunf"
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for {set i 0} {$i < $num_of_converters} {incr i} {
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create_bd_pin -dir O "${ip_name}/dac_enable_${i}"
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create_bd_pin -dir O "${ip_name}/dac_valid_${i}"
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create_bd_pin -dir I "${ip_name}/dac_data_${i}"
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}
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# Generic TPL core
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ad_ip_instance ad_ip_jesd204_tpl_dac "${ip_name}/tpl_core" [list \
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NUM_LANES $num_of_lanes \
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NUM_CHANNELS $num_of_converters \
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SAMPLES_PER_FRAME $samples_per_frame \
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CONVERTER_RESOLUTION $sample_width \
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BITS_PER_SAMPLE $sample_width \
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OCTETS_PER_BEAT $tpl_bytes_per_beat \
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]
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# Concatenation and slicer cores
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ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
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NUM_PORTS $num_of_converters \
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]
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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# Create connections
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# TPL configuration interface
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tpl_core/s_axi_aclk"
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ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tpl_core/s_axi_aresetn"
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ad_connect "${ip_name}/s_axi" "${ip_name}/tpl_core/s_axi"
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# TPL - link layer
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ad_connect ${ip_name}/tpl_core/link_clk ${ip_name}/link_clk
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ad_connect ${ip_name}/tpl_core/link ${ip_name}/link
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# TPL - app layer
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/dac_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/dac_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/dac_valid_$i
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ad_connect ${ip_name}/dac_data_$i ${ip_name}/data_concat/In$i
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}
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ad_connect ${ip_name}/data_concat/dout ${ip_name}/tpl_core/dac_ddata
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ad_connect ${ip_name}/dac_dunf ${ip_name}/tpl_core/dac_dunf
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} resulttext resultoptions]
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dict unset resultoptions -level
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endgroup
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if {$result != 0} {
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undo -quiet
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}
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return -options $resultoptions $resulttext
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}
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# L M S N & NP
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proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width} {
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set link_layer_bytes_per_beat 4
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if {$num_of_lanes < 1 || $num_of_lanes > 8} {
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return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-8)"
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}
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# F = (M * N * S) / (L * 8)
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set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)];
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# one beat per lane must accommodate at least one frame
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set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)]
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# datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N)
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set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)];
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startgroup
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set result [catch {
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create_bd_cell -type hier $ip_name
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# Control interface
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create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
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create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
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# Interface to link layer
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create_bd_pin -dir I -type clk "${ip_name}/link_clk"
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#create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link"
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create_bd_pin -dir I "${ip_name}/link_sof"
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create_bd_pin -dir I "${ip_name}/link_valid"
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create_bd_pin -dir I "${ip_name}/link_data"
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# Interface to application layer
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create_bd_pin -dir I "${ip_name}/adc_dovf"
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for {set i 0} {$i < $num_of_converters} {incr i} {
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create_bd_pin -dir O "${ip_name}/adc_enable_${i}"
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create_bd_pin -dir O "${ip_name}/adc_valid_${i}"
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create_bd_pin -dir O "${ip_name}/adc_data_${i}"
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}
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# Generic TPL core
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ad_ip_instance ad_ip_jesd204_tpl_adc "${ip_name}/tpl_core" [list \
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NUM_LANES $num_of_lanes \
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NUM_CHANNELS $num_of_converters \
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SAMPLES_PER_FRAME $samples_per_frame \
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CONVERTER_RESOLUTION $sample_width \
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BITS_PER_SAMPLE $sample_width \
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OCTETS_PER_BEAT $tpl_bytes_per_beat \
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]
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# Slicer cores
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
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DIN_WIDTH [expr $sample_width*$samples_per_channel*$num_of_converters] \
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DIN_FROM [expr $sample_width*$samples_per_channel*($i+1)-1] \
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DIN_TO [expr $sample_width*$samples_per_channel*$i] \
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]
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ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
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DIN_WIDTH $num_of_converters \
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DIN_FROM $i \
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DIN_TO $i \
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]
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}
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# Create connections
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# TPL configuration interface
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tpl_core/s_axi_aclk"
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ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tpl_core/s_axi_aresetn"
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ad_connect "${ip_name}/s_axi" "${ip_name}/tpl_core/s_axi"
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# TPL - link layer
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ad_connect ${ip_name}/tpl_core/link_clk ${ip_name}/link_clk
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#ad_connect ${ip_name}/tpl_core/link ${ip_name}/link
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ad_connect ${ip_name}/tpl_core/link_sof ${ip_name}/link_sof
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ad_connect ${ip_name}/tpl_core/link_data ${ip_name}/link_data
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ad_connect ${ip_name}/tpl_core/link_valid ${ip_name}/link_valid
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# TPL - app layer
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for {set i 0} {$i < $num_of_converters} {incr i} {
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ad_connect ${ip_name}/tpl_core/adc_data ${ip_name}/data_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/enable ${ip_name}/enable_slice_$i/Din
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ad_connect ${ip_name}/tpl_core/adc_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/data_slice_$i/Dout ${ip_name}/adc_data_$i
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/adc_enable_$i
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ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/adc_valid_$i
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}
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ad_connect ${ip_name}/adc_dovf ${ip_name}/tpl_core/adc_dovf
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} resulttext resultoptions]
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dict unset resultoptions -level
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endgroup
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if {$result != 0} {
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undo -quiet
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}
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return -options $resultoptions $resulttext
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}
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