daq1: Add CPLD logic and IO constraints
Istvan Csomortani
parent
2bb19be3d3
commit
02cc926275
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "adc_fda" LOC = "P6" | IOSTANDARD = LVCMOS33 ;
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NET "adc_fdb" LOC = "P7" | IOSTANDARD = LVCMOS33 ;
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NET "adc_pwdn_stby" LOC = "P10" | IOSTANDARD = LVCMOS33 ;
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NET "adc_spicsn" LOC = "P13" | IOSTANDARD = LVCMOS33 ;
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NET "adc_status_n" LOC = "P9" | IOSTANDARD = LVCMOS33 ;
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NET "adc_status_p" LOC = "P8" | IOSTANDARD = LVCMOS33 ;
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NET "clk_pwdnn" LOC = "P20" | IOSTANDARD = LVCMOS33 ;
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NET "clk_resetn" LOC = "P25" | IOSTANDARD = LVCMOS33 ;
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NET "clk_spicsn" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
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NET "clk_status1" LOC = "P17" | IOSTANDARD = LVCMOS33 ;
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NET "clk_status2" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
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NET "clk_syncn" LOC = "P24" | IOSTANDARD = LVCMOS33 ;
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NET "dac_irqn" LOC = "P26" | IOSTANDARD = LVCMOS33 ;
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NET "dac_resetn" LOC = "P27" | IOSTANDARD = LVCMOS33 ;
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NET "dac_spicsn" LOC = "P14" | IOSTANDARD = LVCMOS33 ;
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NET "fmc_irq" LOC = "P5" | IOSTANDARD = LVCMOS25 ;
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NET "fmc_spi_csn" LOC = "P2" | IOSTANDARD = LVCMOS25 ;
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NET "fmc_spi_sclk" LOC = "P1" | IOSTANDARD = LVCMOS25;
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NET "fmc_spi_sdio" LOC = "P4" | IOSTANDARD = LVCMOS25 ;
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NET "sclk" LOC = "P30" | IOSTANDARD = LVCMOS33 ;
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NET "sdio" LOC = "P28" | IOSTANDARD = LVCMOS33 ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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@ -0,0 +1,271 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module daq1_cpld (
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// FMC SPI interface
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fmc_spi_sclk,
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fmc_spi_csn,
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fmc_spi_sdio,
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fmc_irq,
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// on board SPI interface
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adc_spicsn,
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dac_spicsn,
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clk_spicsn,
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sclk,
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sdio,
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// control and status lines
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adc_fda,
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adc_fdb,
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adc_status_p,
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adc_status_n,
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adc_pwdn_stby,
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dac_irqn,
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dac_resetn,
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clk_status1,
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clk_status2,
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clk_pwdnn,
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clk_syncn,
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clk_resetn
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);
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input fmc_spi_csn;
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input fmc_spi_sclk;
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inout fmc_spi_sdio;
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output fmc_irq;
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output adc_spicsn;
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output dac_spicsn;
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output clk_spicsn;
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output sclk;
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inout sdio;
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// control and status lines
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input adc_fda;
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input adc_fdb;
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input adc_status_p;
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input adc_status_n;
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output adc_pwdn_stby;
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input dac_irqn;
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output dac_resetn;
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input clk_status1;
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input clk_status2;
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output clk_pwdnn;
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output clk_syncn;
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output clk_resetn;
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// FMC SPI Selects
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localparam [ 7:0] FMC_SPI_SEL_AD9684 = 8'h80;
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localparam [ 7:0] FMC_SPI_SEL_AD9122 = 8'h81;
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localparam [ 7:0] FMC_SPI_SEL_AD9523 = 8'h82;
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localparam [ 7:0] FMC_SPI_SEL_CPLD = 8'h83;
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// CPLD Register Map Addresses
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localparam [ 6:0] ADC_CONTROL_ADDR = 7'h00;
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localparam [ 6:0] DAC_CONTROL_ADDR = 7'h01;
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localparam [ 6:0] CLK_CONTROL_ADDR = 7'h02;
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localparam [ 6:0] ADC_STATUS_ADDR = 7'h10;
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localparam [ 6:0] DAC_STATUS_ADDR = 7'h11;
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localparam [ 6:0] CLK_STATUS_ADDR = 7'h12;
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// Internal Registers/Signals
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reg [ 7:0] fmc_spi_dev_sel = 8'b0;
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reg [ 7:0] fmc_cpld_addr = 8'b0;
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reg [ 5:0] fmc_spi_counter = 6'b0;
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reg fmc_spi_csn_enb = 1'b1;
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reg [ 7:0] adc_control = 8'b0;
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reg [ 7:0] dac_control = 8'b0;
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reg [ 7:0] clk_control = 8'b0;
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reg [ 7:0] adc_status = 8'b0;
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reg [ 7:0] dac_status = 8'b0;
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reg [ 7:0] clk_status = 8'b0;
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reg fpga_to_cpld = 1'b1;
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reg [ 7:0] cpld_rdata = 8'b0;
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reg cpld_rdata_bit = 1'b0;
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reg [ 2:0] cpld_rdata_index = 3'h0;
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reg [ 7:0] cpld_wdata = 8'b0;
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wire rdnwr;
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wire cpld_rdata_s;
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// SCLK counter for control signals
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always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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fmc_spi_counter <= 6'h0;
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fmc_spi_dev_sel <= 8'h0;
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fmc_cpld_addr <= 8'h0;
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end else begin
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fmc_spi_counter <= fmc_spi_counter + 1;
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if (fmc_spi_counter <= 7) begin
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fmc_spi_dev_sel <= {fmc_spi_dev_sel[6:0], fmc_spi_sdio};
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end
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if (fmc_spi_counter <= 15) begin
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fmc_cpld_addr <= {fmc_cpld_addr[6:0], fmc_spi_sdio};
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end
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end
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end
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// chip select control
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assign adc_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9684) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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assign dac_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9122) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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assign clk_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_AD9523) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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assign cpld_spicsn = (fmc_spi_dev_sel == FMC_SPI_SEL_CPLD) ? (fmc_spi_csn | fmc_spi_csn_enb) : 1'b1;
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// SPI control and data
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assign sclk = fmc_spi_sclk;
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assign sdio = fpga_to_cpld ? fmc_spi_sdio : 1'bZ;
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assign fmc_spi_sdio = fpga_to_cpld ? 1'bZ : cpld_rdata_s;
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assign cpld_rdata_s = cpld_spicsn ? sdio : cpld_rdata_bit;
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assign rdnwr = ~fmc_cpld_addr[7];
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always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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fpga_to_cpld <= 1'b1;
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fmc_spi_csn_enb <= 1'b1;
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end else begin
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fmc_spi_csn_enb <= (fmc_spi_counter <= 7) ? 1'b1 : 1'b0;
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if (adc_spicsn & clk_spicsn) begin
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fpga_to_cpld <= (fmc_spi_counter >= 16) ? rdnwr : 1'b1;
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end else begin
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fpga_to_cpld <= (fmc_spi_counter >= 24) ? rdnwr : 1'b1;
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end
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end
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end
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// Internal register read access
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always @(fmc_cpld_addr) begin
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case (fmc_cpld_addr[6:0])
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ADC_CONTROL_ADDR :
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cpld_rdata <= adc_pwdn_stby;
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DAC_CONTROL_ADDR :
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cpld_rdata <= dac_resetn;
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CLK_CONTROL_ADDR :
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cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn};
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ADC_STATUS_ADDR :
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cpld_rdata <= {adc_status_p, adc_fdb, adc_fda};
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DAC_STATUS_ADDR :
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cpld_rdata <= dac_irqn;
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CLK_STATUS_ADDR :
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cpld_rdata <= {clk_status2, clk_status1};
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default:
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cpld_rdata <= 8'hFA;
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endcase
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end
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always @(negedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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cpld_rdata_bit <= 1'b0;
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cpld_rdata_index <= 3'h0;
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end else begin
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if (fpga_to_cpld == 1'b0) begin
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cpld_rdata_bit <= cpld_rdata[cpld_rdata_index];
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cpld_rdata_index <= cpld_rdata_index + 1;
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end
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end
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end
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// Internal register write access
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always @(negedge fmc_spi_sclk) begin
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if ((fpga_to_cpld == 1'b1) &&
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(cpld_spicsn == 1'b0) &&
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(fmc_spi_counter == 8'h18)) begin
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case (fmc_cpld_addr[6:0])
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ADC_CONTROL_ADDR :
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adc_control <= cpld_wdata;
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DAC_CONTROL_ADDR :
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dac_control <= cpld_wdata;
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CLK_CONTROL_ADDR :
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clk_control <= cpld_wdata;
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endcase
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end
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end
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always @(posedge fmc_spi_sclk or posedge fmc_spi_csn) begin
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if (fmc_spi_csn == 1'b1) begin
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cpld_wdata <= 8'h0;
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end else begin
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if (fmc_spi_counter >= 16) begin
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cpld_wdata <= {cpld_wdata[6:0], fmc_spi_sdio};
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end
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end
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end
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// input/output logic
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// AD9648
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assign adc_pwdn_stby = adc_control[0];
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// AD9122
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assign dac_resetn = dac_control[0];
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// AD9523-1
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assign clk_pwdnn = clk_control[0];
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assign clk_resetn = clk_control[1];
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assign clk_syncn = clk_control[2];
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assign fmc_irq = dac_irqn;
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endmodule
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