From 0260280db18b0dcf599e0295b252431407a6318f Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 28 Apr 2016 11:37:46 -0400 Subject: [PATCH] common/altera- data path --- library/common/altera/ad_cmos_in.v | 106 ++-------------------------- library/common/altera/ad_cmos_out.v | 75 +++----------------- library/common/altera/ad_lvds_in.v | 52 ++++++-------- library/common/altera/ad_lvds_out.v | 65 ++++++++++------- 4 files changed, 76 insertions(+), 222 deletions(-) diff --git a/library/common/altera/ad_cmos_in.v b/library/common/altera/ad_cmos_in.v index cf2081778..9737e4021 100644 --- a/library/common/altera/ad_cmos_in.v +++ b/library/common/altera/ad_cmos_in.v @@ -65,8 +65,6 @@ module ad_cmos_in ( parameter DEVICE_TYPE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; // data interface @@ -88,107 +86,17 @@ module ad_cmos_in ( input delay_rst; output delay_locked; - // internal registers + // defaults - reg rx_data_n; - - // internal signals - - wire rx_data_n_s; - wire rx_data_ibuf_s; - wire rx_data_idelay_s; - - // delay controller - - generate - if (IODELAY_CTRL == 1) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end else begin + assign up_drdata = 5'd0; assign delay_locked = 1'b1; - end - endgenerate - // receive data interface, ibuf -> idelay -> iddr + // instantiations - IBUF i_rx_data_ibuf ( - .I (rx_data_in), - .O (rx_data_ibuf_s)); - - generate - if (DEVICE_TYPE == VIRTEX6) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IODELAYE1 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("I"), - .HIGH_PERFORMANCE_MODE ("TRUE"), - .IDELAY_TYPE ("VAR_LOADABLE"), - .IDELAY_VALUE (0), - .ODELAY_TYPE ("FIXED"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .T (1'b1), - .CE (1'b0), - .INC (1'b0), - .CLKIN (1'b0), - .DATAIN (1'b0), - .ODATAIN (1'b0), - .CINVCTRL (1'b0), - .C (up_clk), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .RST (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end else begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("IDATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .IDELAY_TYPE ("VAR_LOAD"), - .IDELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_rx_data_idelay ( - .CE (1'b0), - .INC (1'b0), - .DATAIN (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .IDATAIN (rx_data_ibuf_s), - .DATAOUT (rx_data_idelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end - endgenerate - - IDDR #( - .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), - .INIT_Q1 (1'b0), - .INIT_Q2 (1'b0), - .SRTYPE ("ASYNC")) - i_rx_data_iddr ( - .CE (1'b1), - .R (1'b0), - .S (1'b0), - .C (rx_clk), - .D (rx_data_idelay_s), - .Q1 (rx_data_p), - .Q2 (rx_data_n_s)); - - always @(posedge rx_clk) begin - rx_data_n <= rx_data_n_s; - end + alt_cmos_in i_rx_data_iddr ( + .ck (rx_clk), + .pad_in (rx_data_in), + .dout ({rx_data_p, rx_data_n})); endmodule diff --git a/library/common/altera/ad_cmos_out.v b/library/common/altera/ad_cmos_out.v index 9537d6dd1..4f877f0bb 100644 --- a/library/common/altera/ad_cmos_out.v +++ b/library/common/altera/ad_cmos_out.v @@ -66,8 +66,6 @@ module ad_cmos_out ( parameter IODELAY_ENABLE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; // data interface @@ -89,74 +87,17 @@ module ad_cmos_out ( input delay_rst; output delay_locked; - // internal signals + // defaults - wire tx_data_oddr_s; - wire tx_data_odelay_s; - - // delay controller - - generate - if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - IDELAYCTRL i_delay_ctrl ( - .RST (delay_rst), - .REFCLK (delay_clk), - .RDY (delay_locked)); - end else begin - assign delay_locked = 1'b1; - end - endgenerate - - // transmit data interface, oddr -> odelay -> obuf - - ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE"), - .INIT (1'b0), - .SRTYPE ("ASYNC")) - i_tx_data_oddr ( - .CE (1'b1), - .R (1'b0), - .S (1'b0), - .C (tx_clk), - .D1 (tx_data_p), - .D2 (tx_data_n), - .Q (tx_data_oddr_s)); - - generate - if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin - (* IODELAY_GROUP = IODELAY_GROUP *) - ODELAYE2 #( - .CINVCTRL_SEL ("FALSE"), - .DELAY_SRC ("ODATAIN"), - .HIGH_PERFORMANCE_MODE ("FALSE"), - .ODELAY_TYPE ("VAR_LOAD"), - .ODELAY_VALUE (0), - .REFCLK_FREQUENCY (200.0), - .PIPE_SEL ("FALSE"), - .SIGNAL_PATTERN ("DATA")) - i_tx_data_odelay ( - .CE (1'b0), - .CLKIN (1'b0), - .INC (1'b0), - .LDPIPEEN (1'b0), - .CINVCTRL (1'b0), - .REGRST (1'b0), - .C (up_clk), - .ODATAIN (tx_data_oddr_s), - .DATAOUT (tx_data_odelay_s), - .LD (up_dld), - .CNTVALUEIN (up_dwdata), - .CNTVALUEOUT (up_drdata)); - end else begin assign up_drdata = 5'd0; - assign tx_data_odelay_s = tx_data_oddr_s; - end - endgenerate + assign delay_locked = 1'b1; - OBUF i_tx_data_obuf ( - .I (tx_data_odelay_s), - .O (tx_data_out)); + // instantiations + + alt_cmos_out i_tx_data_oddr ( + .ck (tx_clk), + .din ({tx_data_p, tx_data_n}), + .pad_out (tx_data_out)); endmodule diff --git a/library/common/altera/ad_lvds_in.v b/library/common/altera/ad_lvds_in.v index 7ab54045e..1313e52f8 100644 --- a/library/common/altera/ad_lvds_in.v +++ b/library/common/altera/ad_lvds_in.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -49,22 +47,25 @@ module ad_lvds_in ( rx_data_p, rx_data_n, - // delay interface + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface delay_clk, delay_rst, - delay_ld, - delay_wdata, - delay_rdata, delay_locked); // parameters + parameter SINGLE_ENDED = 0; parameter DEVICE_TYPE = 0; parameter IODELAY_CTRL = 0; parameter IODELAY_GROUP = "dev_if_delay_group"; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; // data interface @@ -74,38 +75,31 @@ module ad_lvds_in ( output rx_data_p; output rx_data_n; - // delay interface + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface input delay_clk; input delay_rst; - input delay_ld; - input [ 4:0] delay_wdata; - output [ 4:0] delay_rdata; output delay_locked; // defaults - assign delay_rdata = 5'd0; + assign up_drdata = 5'd0; assign delay_locked = 1'b1; // instantiations - altddio_in #( - .invert_input_clocks("OFF"), - .lpm_hint("UNUSED"), - .lpm_type("altddio_in"), - .power_up_high("OFF"), - .width(1)) - i_rx_data_iddr ( - .aclr (1'b0), - .aset (1'b0), - .sclr (1'b0), - .sset (1'b0), - .inclocken (1'b1), - .inclock (rx_clk), - .datain (rx_data_in_p), - .dataout_h (rx_data_p), - .dataout_l (rx_data_n)); + alt_lvds_in i_rx_data_iddr ( + .ck (rx_clk), + .pad_in (rx_data_in_p), + .pad_in_b (rx_data_in_n), + .dout ({rx_data_p, rx_data_n})); endmodule diff --git a/library/common/altera/ad_lvds_out.v b/library/common/altera/ad_lvds_out.v index edc756114..05e8a87bc 100644 --- a/library/common/altera/ad_lvds_out.v +++ b/library/common/altera/ad_lvds_out.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -47,13 +45,28 @@ module ad_lvds_out ( tx_data_p, tx_data_n, tx_data_out_p, - tx_data_out_n); + tx_data_out_n, + + // delay-data interface + + up_clk, + up_dld, + up_dwdata, + up_drdata, + + // delay-cntrl interface + + delay_clk, + delay_rst, + delay_locked); // parameters parameter DEVICE_TYPE = 0; - localparam SERIES7 = 0; - localparam VIRTEX6 = 1; + parameter SINGLE_ENDED = 0; + parameter IODELAY_ENABLE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; // data interface @@ -63,33 +76,31 @@ module ad_lvds_out ( output tx_data_out_p; output tx_data_out_n; + // delay-data interface + + input up_clk; + input up_dld; + input [ 4:0] up_dwdata; + output [ 4:0] up_drdata; + + // delay-cntrl interface + + input delay_clk; + input delay_rst; + output delay_locked; + // defaults - assign tx_data_out_n = 1'd0; + assign up_drdata = 5'd0; + assign delay_locked = 1'b1; // instantiations - altddio_out #( - .extend_oe_disable("OFF"), - .intended_device_family("Cyclone V"), - .invert_output("OFF"), - .lpm_hint("UNUSED"), - .lpm_type("altddio_out"), - .oe_reg("UNREGISTERED"), - .power_up_high("OFF"), - .width(1)) - i_tx_data_oddr ( - .aclr (1'b0), - .aset (1'b0), - .sclr (1'b0), - .sset (1'b0), - .oe (1'b1), - .oe_out (), - .outclocken (1'b1), - .outclock (tx_clk), - .datain_h (tx_data_p), - .datain_l (tx_data_n), - .dataout (tx_data_out_p)); + alt_lvds_out i_tx_data_oddr ( + .ck (tx_clk), + .din ({tx_data_p, tx_data_n}), + .pad_out (tx_data_out_p), + .pad_out_b (tx_data_out_n)); endmodule