zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad_ip_jesd204_tpl_dac: added xbar for user channels (dma data) 

Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.

The feature is selectable with synthesis parameter and disabled by default.
main
Laszlo Nagy 2020-03-09 15:58:26 +00:00 committed by Laszlo Nagy
parent 5c561665b0
commit 01f4576fcd
7 changed files with 77 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/jesd204/ad_ip_jesd204_tpl_dac/Makefile
View File

@ -5,6 +5,8 @@
LIBRARY_NAME := ad_ip_jesd204_tpl_dac
GENERIC_DEPS += ../../common/ad_mux.v
GENERIC_DEPS += ../../common/ad_mux_core.v
GENERIC_DEPS += ../../common/ad_dds.v
GENERIC_DEPS += ../../common/ad_dds_1.v
GENERIC_DEPS += ../../common/ad_dds_2.v

15
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
View File

@ -40,7 +40,8 @@ module ad_ip_jesd204_tpl_dac #(
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter EXT_SYNC = 0
parameter EXT_SYNC = 0,
parameter XBAR_ENABLE = 0
) (
// jesd interface
// link_clk is (line-rate/40)
@ -112,9 +113,11 @@ module ad_ip_jesd204_tpl_dac #(
wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s;
wire [NUM_CHANNELS*4-1:0] dac_data_sel_s;
wire [NUM_CHANNELS-1:0] dac_mask_enable_s;
wire [NUM_CHANNELS-1:0] dac_iqcor_enb;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2;
wire [NUM_CHANNELS*8-1:0] dac_src_chan_sel;
// regmap
@ -122,6 +125,7 @@ module ad_ip_jesd204_tpl_dac #(
.ID (ID),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.XBAR_ENABLE (XBAR_ENABLE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -170,11 +174,14 @@ module ad_ip_jesd204_tpl_dac #(
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_mask_enable (dac_mask_enable_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
.dac_src_chan_sel (dac_src_chan_sel),
.jesd_m (NUM_CHANNELS),
.jesd_l (NUM_LANES),
.jesd_s (SAMPLES_PER_FRAME),
@ -189,6 +196,7 @@ module ad_ip_jesd204_tpl_dac #(
ad_ip_jesd204_tpl_dac_core #(
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.XBAR_ENABLE (XBAR_ENABLE),
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
@ -228,10 +236,13 @@ module ad_ip_jesd204_tpl_dac #(
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_mask_enable (dac_mask_enable_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2)
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
.dac_src_chan_sel (dac_src_chan_sel)
);

20
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
View File

@ -52,6 +52,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
input dac_dds_format,
input [3:0] dac_data_sel,
input dac_mask_enable,
input [15:0] dac_dds_scale_0,
input [15:0] dac_dds_init_0,
@ -127,15 +128,16 @@ module ad_ip_jesd204_tpl_dac_channel #(
// dac data select
always @(posedge clk) begin
dac_enable <= (dac_data_sel == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel)
4'h7: dac_data <= pn15_data;
4'h6: dac_data <= pn7_data;
4'h5: dac_data <= ~pn15_data;
4'h4: dac_data <= ~pn7_data;
4'h3: dac_data <= 'h00;
4'h2: dac_data <= dac_iqcor_data_s;
4'h1: dac_data <= dac_pat_data_s;
dac_enable <= dac_mask_enable ? 1'b0 : (dac_data_sel == 4'h2);
casex ({dac_mask_enable,dac_data_sel})
5'h07: dac_data <= pn15_data;
5'h06: dac_data <= pn7_data;
5'h05: dac_data <= ~pn15_data;
5'h04: dac_data <= ~pn7_data;
5'h03: dac_data <= 'h00;
5'h02: dac_data <= dac_iqcor_data_s;
5'h01: dac_data <= dac_pat_data_s;
5'h1x: dac_data <= dac_iqcor_data_s;
default: dac_data <= dac_dds_data_s;
endcase
end

29
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
View File

@ -26,6 +26,7 @@
module ad_ip_jesd204_tpl_dac_core #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter XBAR_ENABLE = 1,
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter BITS_PER_SAMPLE = 16,
@ -62,6 +63,7 @@ module ad_ip_jesd204_tpl_dac_core #(
input dac_dds_format,
input [NUM_CHANNELS*4-1:0] dac_data_sel,
input [NUM_CHANNELS-1:0] dac_mask_enable,
input [NUM_CHANNELS*16-1:0] dac_dds_scale_0,
input [NUM_CHANNELS*16-1:0] dac_dds_init_0,
@ -77,6 +79,8 @@ module ad_ip_jesd204_tpl_dac_core #(
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
input [NUM_CHANNELS*8-1:0] dac_src_chan_sel,
output [NUM_CHANNELS-1:0] enable
);
@ -86,6 +90,7 @@ module ad_ip_jesd204_tpl_dac_core #(
wire [DAC_DATA_WIDTH-1:0] dac_data_s;
wire [DMA_DATA_WIDTH-1:0] dac_ddata_muxed;
wire [DAC_CDW-1:0] pn7_data;
wire [DAC_CDW-1:0] pn15_data;
@ -153,6 +158,25 @@ module ad_ip_jesd204_tpl_dac_core #(
localparam IQ_PAIR_CH_INDEX = (NUM_CHANNELS%2) ? i :
(i%2) ? i-1 : i+1;
if (XBAR_ENABLE == 1) begin
// NUM_CHANNELS : 1 mux
ad_mux #(
.CH_W (DMA_CDW),
.CH_CNT (NUM_CHANNELS),
.EN_REG (1)
) channel_mux (
.clk (clk),
.data_in (dac_ddata),
.ch_sel (dac_src_chan_sel[8*i+:8]),
.data_out (dac_ddata_muxed[DMA_CDW*i+:DMA_CDW])
);
end else begin
assign dac_ddata_muxed[DMA_CDW*i+:DMA_CDW] = dac_ddata[DMA_CDW*i+:DMA_CDW];
end
ad_ip_jesd204_tpl_dac_channel #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
@ -167,7 +191,7 @@ module ad_ip_jesd204_tpl_dac_core #(
.clk (clk),
.dac_enable (enable[i]),
.dac_data (dac_data_s[DAC_CDW*i+:DAC_CDW]),
.dma_data (dac_ddata[DMA_CDW*i+:DMA_CDW]),
.dma_data (dac_ddata_muxed[DMA_CDW*i+:DMA_CDW]),
.pn7_data (pn7_data),
.pn15_data (pn15_data),
@ -176,6 +200,7 @@ module ad_ip_jesd204_tpl_dac_core #(
.dac_dds_format (dac_dds_format),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_mask_enable (dac_mask_enable[i]),
.dac_dds_scale_0 (dac_dds_scale_0[16*i+:16]),
.dac_dds_init_0 (dac_dds_init_0[16*i+:16]),
@ -190,7 +215,7 @@ module ad_ip_jesd204_tpl_dac_core #(
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.dac_iqcor_data_in (dac_ddata[DMA_CDW*IQ_PAIR_CH_INDEX+:DMA_CDW])
.dac_iqcor_data_in (dac_ddata_muxed[DMA_CDW*IQ_PAIR_CH_INDEX+:DMA_CDW])
);
end

7
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
View File

@ -29,6 +29,8 @@ ad_ip_create ad_ip_jesd204_tpl_dac "JESD204 Transport Layer for DACs" p_ad_ip_je
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_dac_validate
ad_ip_files ad_ip_jesd204_tpl_dac [list \
$ad_hdl_dir/library/intel/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_mux.v \
$ad_hdl_dir/library/common/ad_mux_core.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
@ -201,6 +203,11 @@ ad_ip_parameter DDS_CORDIC_PHASE_DW INTEGER 16 true [list \
GROUP $group \
]
ad_ip_parameter XBAR_ENABLE boolean 0 true [list \
DISPLAY_NAME "Channel Crossbar Enable" \
GROUP $group \
]
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12

3
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
View File

@ -27,6 +27,8 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create ad_ip_jesd204_tpl_dac
adi_ip_files ad_ip_jesd204_tpl_dac [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_mux.v" \
"$ad_hdl_dir/library/common/ad_mux_core.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
@ -147,6 +149,7 @@ foreach {k v w} {
"DATAPATH_DISABLE" "Disable Datapath" "checkBox" \
"EXT_SYNC" "Enable external SYNC" "checkBox" \
"IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \
"XBAR_ENABLE" "Enable user data XBAR" "checkBox" \
"DDS_TYPE" "DDS Type" "comboBox" \
"DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \
"DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \

16
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
View File

@ -27,6 +27,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter XBAR_ENABLE = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
@ -71,6 +72,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
input dac_sync_in_status,
output [NUM_CHANNELS*4-1:0] dac_data_sel,
output [NUM_CHANNELS-1:0] dac_mask_enable,
output dac_dds_format,
output [NUM_CHANNELS*16-1:0] dac_dds_scale_0,
@ -87,6 +89,8 @@ module ad_ip_jesd204_tpl_dac_regmap #(
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
output [NUM_CHANNELS*8-1:0] dac_src_chan_sel,
// Framer interface
input [NUM_PROFILES*8-1: 0] jesd_m,
input [NUM_PROFILES*8-1: 0] jesd_l,
@ -183,11 +187,15 @@ module ad_ip_jesd204_tpl_dac_regmap #(
end
// dac common processor interface
//
localparam CONFIG = (XBAR_ENABLE << 10) ||
(DATAPATH_DISABLE << 6) ||
(IQCORRECTION_DISABLE << 0);
up_dac_common #(
.COMMON_ID(6'h0),
.ID (ID),
.CONFIG((DATAPATH_DISABLE << 6) | (IQCORRECTION_DISABLE << 0)),
.CONFIG(CONFIG),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
@ -246,8 +254,10 @@ module ad_ip_jesd204_tpl_dac_regmap #(
up_dac_channel #(
.COMMON_ID(6'h1 + i/16),
.CHANNEL_ID (i % 16),
.CHANNEL_NUMBER (i),
.USERPORTS_DISABLE (1),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.XBAR_ENABLE (XBAR_ENABLE)
) i_up_dac_channel (
.dac_clk (link_clk),
.dac_rst (dac_rst),
@ -260,10 +270,12 @@ module ad_ip_jesd204_tpl_dac_regmap #(
.dac_pat_data_1 (dac_pat_data_0[16*i+:16]),
.dac_pat_data_2 (dac_pat_data_1[16*i+:16]),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_mask_enable (dac_mask_enable[i]),
.dac_iq_mode (),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.dac_src_chan_sel (dac_src_chan_sel[8*i+:8]),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),