diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index 9b936e33e..e045e712e 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -55,7 +55,7 @@ ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/qpll_ref_clk_* ad_xcvrpll rx_ref_clk_0 util_ad6676_xcvr/cpll_ref_clk_* ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad6676_xcvr/up_pll_rst util_ad6676_xcvr/up_cpll_rst_* -ad_connect sys_cpu_resetn util_ad6676_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_ad6676_xcvr/up_rstn ad_connect $sys_cpu_clk util_ad6676_xcvr/up_clk # connections (adc) @@ -93,7 +93,7 @@ ad_mem_hp3_interconnect $sys_cpu_clk axi_ad6676_xcvr/m_axi ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect $sys_dma_clk axi_ad6676_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad6676_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad6676_dma/m_dest_axi_aresetn # interrupts diff --git a/projects/ad9208_dual_ebz/common/dual_ad9208_bd.tcl b/projects/ad9208_dual_ebz/common/dual_ad9208_bd.tcl index 97f63ce05..d48db8666 100644 --- a/projects/ad9208_dual_ebz/common/dual_ad9208_bd.tcl +++ b/projects/ad9208_dual_ebz/common/dual_ad9208_bd.tcl @@ -121,8 +121,8 @@ ad_xcvrpll rx_ref_clk_1 util_adc_1_xcvr/cpll_ref_clk_7 ad_xcvrpll axi_ad9208_1_xcvr/up_pll_rst util_adc_1_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad9208_1_xcvr/up_pll_rst util_adc_1_xcvr/up_cpll_rst_* -ad_connect sys_cpu_resetn util_adc_0_xcvr/up_rstn -ad_connect sys_cpu_resetn util_adc_1_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_adc_0_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_adc_1_xcvr/up_rstn ad_connect $sys_cpu_clk util_adc_0_xcvr/up_clk ad_connect $sys_cpu_clk util_adc_1_xcvr/up_clk @@ -159,7 +159,7 @@ ad_connect $sys_cpu_clk axi_ad9208_dma/s_axis_aclk # connect resets ad_connect axi_ad9208_0_jesd_rstgen/peripheral_reset axi_ad9208_fifo/adc_rst ad_connect axi_ad9208_0_jesd_rstgen/peripheral_reset util_ad9208_cpack/reset -ad_connect sys_cpu_resetn axi_ad9208_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9208_dma/m_dest_axi_aresetn # connect dataflow diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index 0770932d8..bfaa485db 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -50,7 +50,7 @@ ad_cpu_interconnect 0x44A30000 axi_ad9265_dma ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect $sys_dma_clk axi_ad9265_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad9265_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9265_dma/m_dest_axi_aresetn # interrupts diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl index 71cf2955e..b234c7113 100644 --- a/projects/ad9434_fmc/common/ad9434_bd.tcl +++ b/projects/ad9434_fmc/common/ad9434_bd.tcl @@ -48,7 +48,7 @@ ad_cpu_interconnect 0x44A30000 axi_ad9434_dma ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect $sys_dma_clk axi_ad9434_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad9434_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9434_dma/m_dest_axi_aresetn # interrupts diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 70276b665..ebb2ad0b6 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -49,7 +49,7 @@ ad_cpu_interconnect 0x44A30000 axi_ad9467_dma ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9467_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad9467_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9467_dma/m_dest_axi_aresetn # interrupts diff --git a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl index d8e410f26..c59321164 100644 --- a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl +++ b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl @@ -51,7 +51,7 @@ ad_cpu_interconnect 0x7c420000 axi_ad9739a_dma ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect $sys_dma_clk axi_ad9739a_dma/m_src_axi -ad_connect sys_cpu_resetn axi_ad9739a_dma/m_src_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9739a_dma/m_src_axi_aresetn # interrupts diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl index 04daab1f1..3a9a8900b 100644 --- a/projects/adrv9371x/common/adrv9371x_bd.tcl +++ b/projects/adrv9371x/common/adrv9371x_bd.tcl @@ -186,7 +186,7 @@ set rx_obs_ref_clk rx_ref_clk_$RX_NUM_OF_LANES create_bd_port -dir I $tx_ref_clk create_bd_port -dir I $rx_ref_clk create_bd_port -dir I $rx_obs_ref_clk -ad_connect sys_cpu_resetn util_ad9371_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_ad9371_xcvr/up_rstn ad_connect $sys_cpu_clk util_ad9371_xcvr/up_clk # Tx @@ -219,13 +219,7 @@ for {set i 0} {$i < $RX_OS_NUM_OF_LANES} {incr i} { # dma clock & reset -ad_ip_instance proc_sys_reset sys_dma_rstgen -ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1 - -ad_connect $sys_dma_clk sys_dma_rstgen/slowest_sync_clk -ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn -ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset -ad_connect sys_dma_reset axi_ad9371_dacfifo/dma_rst +ad_connect $sys_dma_reset axi_ad9371_dacfifo/dma_rst # connections (dac) @@ -258,7 +252,7 @@ ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req ad_connect axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last ad_connect axi_ad9371_dacfifo/dac_dunf tx_ad9371_tpl_core/dac_dunf ad_connect axi_ad9371_dacfifo/bypass dac_fifo_bypass -ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn +ad_connect $sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn # connections (adc) @@ -278,7 +272,7 @@ ad_connect rx_ad9371_tpl_core/adc_dovf util_ad9371_rx_cpack/fifo_wr_overflow ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk ad_connect util_ad9371_rx_cpack/packed_fifo_wr axi_ad9371_rx_dma/fifo_wr -ad_connect sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn +ad_connect $sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn # connections (adc-os) @@ -298,7 +292,7 @@ for {set i 0} {$i < $RX_OS_NUM_OF_CONVERTERS} {incr i} { ad_connect rx_os_ad9371_tpl_core/adc_dovf util_ad9371_rx_os_cpack/fifo_wr_overflow ad_connect util_ad9371_rx_os_cpack/packed_fifo_wr axi_ad9371_rx_os_dma/fifo_wr -ad_connect sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn +ad_connect $sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn # interconnect (cpu) diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl index 30ff622a7..5cadb8a7e 100644 --- a/projects/cn0363/common/cn0363_bd.tcl +++ b/projects/cn0363/common/cn0363_bd.tcl @@ -261,7 +261,7 @@ connect_bd_net -net $sys_cpu_clk \ [get_bd_pins /phase_gen/CLK] \ [get_bd_pins /axi_adc/adc_clk] -connect_bd_net -net sys_cpu_resetn \ +connect_bd_net -net $sys_cpu_resetn \ [get_bd_pins /spi/resetn] \ [get_bd_pins /processing/resetn] \ [get_bd_pins /axi_dma/m_dest_axi_aresetn] diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index e0c13a9ef..7c653a3ba 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -183,6 +183,13 @@ set sys_cpu_clk [get_bd_nets sys_cpu_clk] set sys_dma_clk [get_bd_nets sys_200m_clk] set sys_iodelay_clk [get_bd_nets sys_200m_clk] +set sys_cpu_reset [get_bd_nets sys_cpu_reset] +set sys_cpu_resetn [get_bd_nets sys_cpu_resetn] +set sys_dma_reset [get_bd_nets sys_200m_reset] +set sys_dma_resetn [get_bd_nets sys_200m_resetn] +set sys_iodelay_reset [get_bd_nets sys_200m_reset] +set sys_iodelay_resetn [get_bd_nets sys_200m_resetn] + ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk ad_connect sys_200m_clk sys_200m_rstgen/slowest_sync_clk ad_connect sys_cpu_clk sys_mb/Clk diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 43a631883..1881a34fa 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -123,6 +123,13 @@ set sys_cpu_clk [get_bd_nets sys_cpu_clk] set sys_dma_clk [get_bd_nets sys_200m_clk] set sys_iodelay_clk [get_bd_nets sys_200m_clk] +set sys_cpu_reset [get_bd_nets sys_cpu_reset] +set sys_cpu_resetn [get_bd_nets sys_cpu_resetn] +set sys_dma_reset [get_bd_nets sys_200m_reset] +set sys_dma_resetn [get_bd_nets sys_200m_resetn] +set sys_iodelay_reset [get_bd_nets sys_200m_reset] +set sys_iodelay_resetn [get_bd_nets sys_200m_resetn] + # interface connections ad_connect ddr sys_ps7/DDR diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index af01e00bf..eba159be3 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -86,8 +86,8 @@ ad_ip_parameter util_daq2_xcvr CONFIG.TX_OUT_DIV 1 ad_ip_parameter util_daq2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0104 ad_ip_parameter util_daq2_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020 -ad_connect sys_cpu_resetn util_daq2_xcvr/up_rstn -ad_connect sys_cpu_clk util_daq2_xcvr/up_clk +ad_connect $sys_cpu_resetn util_daq2_xcvr/up_rstn +ad_connect $sys_cpu_clk util_daq2_xcvr/up_clk # reference clocks & resets @@ -123,10 +123,10 @@ ad_connect axi_ad9144_upack/s_axis_ready axi_ad9144_fifo/dac_valid ad_connect axi_ad9144_upack/s_axis_data axi_ad9144_fifo/dac_data ad_connect axi_ad9144_core/dac_dunf axi_ad9144_fifo/dac_dunf -ad_connect sys_cpu_clk axi_ad9144_fifo/dma_clk -ad_connect sys_cpu_reset axi_ad9144_fifo/dma_rst -ad_connect sys_cpu_clk axi_ad9144_dma/m_axis_aclk -ad_connect sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn +ad_connect $sys_cpu_clk axi_ad9144_fifo/dma_clk +ad_connect $sys_cpu_reset axi_ad9144_fifo/dma_rst +ad_connect $sys_cpu_clk axi_ad9144_dma/m_axis_aclk +ad_connect $sys_cpu_resetn axi_ad9144_dma/m_src_axi_aresetn ad_connect axi_ad9144_fifo/dma_xfer_req axi_ad9144_dma/m_axis_xfer_req ad_connect axi_ad9144_fifo/dma_ready axi_ad9144_dma/m_axis_ready @@ -160,7 +160,7 @@ ad_connect axi_ad9680_cpack/packed_fifo_wr_overflow axi_ad9680_fifo/adc_wovf ad_connect $sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk -ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index d47cc0d7a..e25c5ecf5 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -87,7 +87,7 @@ ad_ip_parameter util_daq3_xcvr CONFIG.TX_OUT_DIV 1 ad_ip_parameter util_daq3_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904 ad_ip_parameter util_daq3_xcvr CONFIG.RX_CDR_CFG 0x0B000023FF10400020 -ad_connect sys_cpu_resetn util_daq3_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_daq3_xcvr/up_rstn ad_connect $sys_cpu_clk util_daq3_xcvr/up_clk # reference clocks & resets @@ -116,9 +116,9 @@ for {set i 0} {$i < 2} {incr i} { if {$sys_zynq == 0 || $sys_zynq == 1} { ad_connect $sys_cpu_clk axi_ad9152_fifo/dma_clk - ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst + ad_connect $sys_cpu_reset axi_ad9152_fifo/dma_rst ad_connect $sys_cpu_clk axi_ad9152_dma/m_axis_aclk - ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn + ad_connect $sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn ad_connect axi_ad9152_fifo/bypass GND } ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk @@ -150,7 +150,7 @@ if {$sys_zynq == 0 || $sys_zynq == 1} { ad_connect axi_ad9680_cpack/packed_fifo_wr_data axi_ad9680_fifo/adc_wdata ad_connect $sys_cpu_clk axi_ad9680_fifo/dma_clk ad_connect $sys_cpu_clk axi_ad9680_dma/s_axis_aclk - ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn + ad_connect $sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index 0cf98e10b..74c278f52 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -53,7 +53,7 @@ ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_* ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_* ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_* -ad_connect sys_cpu_resetn util_fmcadc2_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_fmcadc2_xcvr/up_rstn ad_connect $sys_cpu_clk util_fmcadc2_xcvr/up_clk # connections (adc) @@ -65,7 +65,7 @@ ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/rx_data ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/rx_sof ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk -ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn ad_connect axi_ad9625_core/adc_clk axi_ad9625_fifo/adc_clk ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst ad_connect axi_ad9625_core/adc_enable axi_ad9625_fifo/adc_wr diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index 78d25af26..875592a1f 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -88,8 +88,8 @@ ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/qpll_ref_clk_* ad_xcvrpll rx_ref_clk_1 util_fmcadc5_1_xcvr/cpll_ref_clk_* ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad9625_1_xcvr/up_pll_rst util_fmcadc5_1_xcvr/up_cpll_rst_* -ad_connect sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn -ad_connect sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_fmcadc5_0_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_fmcadc5_1_xcvr/up_rstn ad_connect $sys_cpu_clk util_fmcadc5_0_xcvr/up_clk ad_connect $sys_cpu_clk util_fmcadc5_1_xcvr/up_clk @@ -118,7 +118,7 @@ ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_0_core/adc_dovf ad_connect axi_ad9625_fifo/adc_wovf axi_ad9625_1_core/adc_dovf ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk -ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready @@ -162,7 +162,7 @@ ad_disconnect spi_sdi_i axi_spi/io1_i ad_ip_instance axi_fmcadc5_sync axi_fmcadc5_sync ad_cpu_interconnect 0x44a20000 axi_fmcadc5_sync -ad_connect sys_cpu_reset axi_fmcadc5_sync/delay_rst +ad_connect $sys_cpu_reset axi_fmcadc5_sync/delay_rst ad_connect $sys_iodelay_clk axi_fmcadc5_sync/delay_clk ad_connect util_fmcadc5_0_xcvr/rx_out_clk_0 axi_fmcadc5_sync/rx_clk ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_sync/rx_enable_0 diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index ec2a80b5f..b96f796c3 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -83,7 +83,7 @@ ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/qpll_ref_clk_* ad_xcvrpll rx_ref_clk_0 util_fmcjesdadc1_xcvr/cpll_ref_clk_* ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_* -ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn ad_connect $sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk create_bd_port -dir O rx_core_clk @@ -134,8 +134,8 @@ ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect $sys_dma_clk axi_ad9250_0_dma/m_dest_axi ad_mem_hp2_interconnect $sys_dma_clk axi_ad9250_1_dma/m_dest_axi -ad_connect sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn -ad_connect sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9250_0_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9250_1_dma/m_dest_axi_aresetn #interrupts diff --git a/projects/fmcomms11/common/fmcomms11_bd.tcl b/projects/fmcomms11/common/fmcomms11_bd.tcl index eef34c0f7..0b2663907 100644 --- a/projects/fmcomms11/common/fmcomms11_bd.tcl +++ b/projects/fmcomms11/common/fmcomms11_bd.tcl @@ -119,7 +119,7 @@ ad_xcvrpll tx_ref_clk_0 util_fmcomms11_xcvr/qpll_ref_clk_* ad_xcvrpll rx_ref_clk_0 util_fmcomms11_xcvr/cpll_ref_clk_* ad_xcvrpll axi_ad9162_xcvr/up_pll_rst util_fmcomms11_xcvr/up_qpll_rst_* ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcomms11_xcvr/up_cpll_rst_* -ad_connect sys_cpu_resetn util_fmcomms11_xcvr/up_rstn +ad_connect $sys_cpu_resetn util_fmcomms11_xcvr/up_rstn ad_connect $sys_cpu_clk util_fmcomms11_xcvr/up_clk # connections (dac) @@ -140,13 +140,14 @@ for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { ad_connect util_fmcomms11_xcvr/tx_out_clk_0 axi_ad9162_fifo/dac_clk ad_connect axi_ad9162_jesd_rstgen/peripheral_reset axi_ad9162_fifo/dac_rst ad_connect $sys_cpu_clk axi_ad9162_fifo/dma_clk -ad_connect sys_cpu_reset axi_ad9162_fifo/dma_rst +ad_connect $sys_cpu_reset axi_ad9162_fifo/dma_rst ad_connect $sys_cpu_clk axi_ad9162_dma/m_axis_aclk ad_connect sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn ad_connect util_ad9162_upack/s_axis_valid VCC ad_connect util_ad9162_upack/s_axis_ready axi_ad9162_fifo/dac_valid ad_connect util_ad9162_upack/s_axis_data axi_ad9162_fifo/dac_data ad_connect axi_ad9162_core/dac_dunf axi_ad9162_fifo/dac_dunf +ad_connect $sys_cpu_resetn axi_ad9162_dma/m_src_axi_aresetn ad_connect axi_ad9162_fifo/dma_xfer_req axi_ad9162_dma/m_axis_xfer_req ad_connect axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready ad_connect axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data @@ -169,7 +170,7 @@ ad_connect axi_ad9625_core/adc_valid_0 axi_ad9625_fifo/adc_wr ad_connect axi_ad9625_core/adc_data_0 axi_ad9625_fifo/adc_wdata ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk -ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index febe8b807..a7857b082 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -56,7 +56,7 @@ ad_connect up_txnrx axi_ad9361/up_txnrx ad_ip_instance util_tdd_sync util_ad9361_tdd_sync ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 ad_connect $sys_cpu_clk util_ad9361_tdd_sync/clk -ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect $sys_cpu_resetn util_ad9361_tdd_sync/rstn ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr @@ -142,7 +142,7 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr -ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn # dac-path rfifo @@ -201,7 +201,7 @@ ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk ad_connect axi_ad9361_dac_dma/m_axis util_ad9361_dac_upack/s_axis -ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn # interconnects diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index b66d83805..021de8b76 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -42,7 +42,7 @@ create_bd_port -dir I up_enable_1 create_bd_port -dir I up_txnrx_1 create_bd_port -dir O sys_100m_resetn -ad_connect sys_cpu_resetn sys_100m_resetn +ad_connect $sys_cpu_resetn sys_100m_resetn # ad9361 core (master) @@ -190,7 +190,7 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr -ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn # dac-path rfifo @@ -261,7 +261,7 @@ ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_SRC 64 -ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn +ad_connect $sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk ad_connect axi_ad9361_dac_dma/m_axis util_ad9361_dac_upack/s_axis diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl index 1c7971fe5..0074e2ffa 100644 --- a/projects/imageon/common/imageon_bd.tcl +++ b/projects/imageon/common/imageon_bd.tcl @@ -51,7 +51,7 @@ ad_connect axi_hdmi_rx_core/hdmi_dma_de axi_hdmi_rx_dma/fifo_wr_en ad_connect axi_hdmi_rx_core/hdmi_dma_data axi_hdmi_rx_dma/fifo_wr_din ad_connect axi_hdmi_rx_core/hdmi_dma_ovf axi_hdmi_rx_dma/fifo_wr_overflow ad_connect axi_hdmi_rx_core/hdmi_dma_unf GND -ad_connect sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn +ad_connect $sys_cpu_resetn axi_hdmi_rx_dma/m_dest_axi_aresetn ad_cpu_interconnect 0x43100000 axi_hdmi_rx_core ad_cpu_interconnect 0x43C20000 axi_hdmi_rx_dma @@ -79,9 +79,9 @@ ad_ip_parameter axi_spdif_rx_core CONFIG.C_DMA_TYPE 1 ad_ip_parameter sys_ps7 CONFIG.PCW_USE_DMA3 1 -ad_connect sys_cpu_clk axi_spdif_rx_core/DMA_REQ_ACLK -ad_connect sys_cpu_clk sys_ps7/DMA3_ACLK -ad_connect sys_cpu_resetn axi_spdif_rx_core/DMA_REQ_RSTN +ad_connect $sys_cpu_clk axi_spdif_rx_core/DMA_REQ_ACLK +ad_connect $sys_cpu_clk sys_ps7/DMA3_ACLK +ad_connect $sys_cpu_resetn axi_spdif_rx_core/DMA_REQ_RSTN ad_connect sys_ps7/DMA3_REQ axi_spdif_rx_core/DMA_REQ ad_connect sys_ps7/DMA3_ACK axi_spdif_rx_core/DMA_ACK ad_connect spdif_rx axi_spdif_rx_core/spdif_rx_i diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index af92de5df..8a3864f51 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -212,7 +212,7 @@ ad_connect $sys_cpu_clk current_monitor_m1_pack/clk - ad_connect sys_cpu_reset current_monitor_m1_pack/reset + ad_connect $sys_cpu_reset current_monitor_m1_pack/reset ad_connect current_monitor_m1/adc_enable_ia current_monitor_m1_pack/enable_0 ad_connect current_monitor_m1/adc_enable_ib current_monitor_m1_pack/enable_1 @@ -235,7 +235,7 @@ ad_connect adc_m2_vbus_dat_i current_monitor_m2/adc_vbus_dat_i ad_connect $sys_cpu_clk current_monitor_m2_pack/clk - ad_connect sys_cpu_reset current_monitor_m2_pack/reset + ad_connect $sys_cpu_reset current_monitor_m2_pack/reset ad_connect current_monitor_m2/adc_enable_ia current_monitor_m2_pack/enable_0 ad_connect current_monitor_m2/adc_enable_ib current_monitor_m2_pack/enable_1 @@ -288,7 +288,7 @@ # ethernet - ad_connect sys_cpu_resetn eth_phy_rst_n + ad_connect $sys_cpu_resetn eth_phy_rst_n ad_connect sys_ps7/ENET0_MDIO_MDC eth_mdio_mdc ad_connect sys_ps7/ENET0_MDIO_O eth_mdio_o ad_connect sys_ps7/ENET0_MDIO_T eth_mdio_t @@ -324,11 +324,11 @@ # iic ad_connect iic_ee2/IIC iic_ee2 - ad_connect sys_cpu_resetn speed_detector_m1_dma/m_dest_axi_aresetn - ad_connect sys_cpu_resetn speed_detector_m2_dma/m_dest_axi_aresetn - ad_connect sys_cpu_resetn current_monitor_m1_dma/m_dest_axi_aresetn - ad_connect sys_cpu_resetn current_monitor_m2_dma/m_dest_axi_aresetn - ad_connect sys_cpu_resetn xadc_core/s_axi_aresetn + ad_connect $sys_cpu_resetn speed_detector_m1_dma/m_dest_axi_aresetn + ad_connect $sys_cpu_resetn speed_detector_m2_dma/m_dest_axi_aresetn + ad_connect $sys_cpu_resetn current_monitor_m1_dma/m_dest_axi_aresetn + ad_connect $sys_cpu_resetn current_monitor_m2_dma/m_dest_axi_aresetn + ad_connect $sys_cpu_resetn xadc_core/s_axi_aresetn # address map ad_cpu_interconnect 0x40410000 speed_detector_m1