From 0064004d34713b34988a667e017095ab53011c30 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 2 Oct 2017 20:15:06 +0300 Subject: [PATCH] axi_dmac: Control s_axis_user/fifo_wr_sync validity The ports s_axis_user or fifo_wr_sync will be active just if the SYNC_TRANSFER_START is enabled. --- library/axi_dmac/axi_dmac_hw.tcl | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl index 0dc86cd85..1cf696723 100644 --- a/library/axi_dmac/axi_dmac_hw.tcl +++ b/library/axi_dmac/axi_dmac_hw.tcl @@ -333,9 +333,6 @@ ad_alt_intf signal s_axis_ready output 1 ready ad_alt_intf signal s_axis_xfer_req output 1 xfer_req ad_alt_intf signal s_axis_user input 1 user -set_port_property s_axis_user termination true -set_port_property s_axis_user termination_value 1 - # fifo destination/source ad_alt_intf clock fifo_rd_clk input 1 clk @@ -386,6 +383,12 @@ proc axi_dmac_elaborate {} { if_s_axis_xfer_req if_s_axis_user } + if {[get_parameter_value DMA_TYPE_SRC] == 1 && + [get_parameter_value SYNC_TRANSFER_START] == 0} { + set_port_property s_axis_user termination true + set_port_property s_axis_user termination_value 1 + } + # fifo destination/source if {[get_parameter_value DMA_TYPE_DEST] != 2} { @@ -400,6 +403,12 @@ proc axi_dmac_elaborate {} { if_fifo_wr_sync if_fifo_wr_xfer_req } + if {[get_parameter_value DMA_TYPE_SRC] == 2 && + [get_parameter_value SYNC_TRANSFER_START] == 0} { + set_port_property fifo_wr_sync termination true + set_port_property fifo_wr_sync termination_value 1 + } + foreach intf $disabled_intfs { set_interface_property $intf ENABLED false }