fmcjesdadc1/a10gx- fix sysref, gpio connections
parent
dba419239b
commit
004aee930b
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@ -4,6 +4,7 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -to [get_registers *sysref_en_m1*]
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
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set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
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@ -80,7 +80,7 @@ module system_top (
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// lane interface
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input ref_clk,
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input rx_sysref,
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output rx_sysref,
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output rx_sync,
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input [ 3:0] rx_data,
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@ -105,10 +105,6 @@ module system_top (
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wire spi_mosi;
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wire [ 7:0] spi_csn_s;
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// gpio in & out are separate cores
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assign gpio_i[63:32] = gpio_o[63:32];
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// board stuff
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assign eth_resetn = ~eth_reset;
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@ -117,13 +113,16 @@ module system_top (
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assign ddr3_a[14:12] = 3'd0;
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assign gpio_i[63:32] = gpio_o[63:32];
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assign gpio_i[31:27] = gpio_o[31:27];
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assign gpio_i[26:16] = gpio_bd_i;
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assign gpio_i[15: 0] = gpio_o[15:0];
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assign gpio_bd_o = gpio_o[15:0];
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assign spi_csn = spi_csn_s[0];
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// instantiations
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assign spi_csn = spi_csn_s[0];
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn_s[0]),
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.spi_clk (spi_clk),
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@ -131,6 +130,11 @@ module system_top (
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
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.core_clk (rx_clk),
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.sysref_en (gpio_o[32]),
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.sysref_out (rx_sysref));
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system_bd i_system_bd (
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.rx_core_clk_clk (rx_clk),
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.rx_data_0_rx_serial_data (rx_data[0]),
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@ -184,7 +188,7 @@ module system_top (
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_rst_reset_n (sys_resetn),
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.sys_spi_MISO (spi_miso),
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.sys_spi_MOSI (spi_mosi_s),
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s));
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