jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters
parent
db573a59b0
commit
002f8d8a3e
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@ -68,8 +68,8 @@ adi_add_bus "link" "master" \
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adi_add_bus_clock "link_clk" "link"
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adi_add_bus_clock "link_clk" "link"
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foreach {p v} {
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foreach {p v} {
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"NUM_LANES" "1 2 3 4 8" \
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"NUM_LANES" "1 2 3 4 8 16" \
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"NUM_CHANNELS" "1 2 4 6 8" \
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"NUM_CHANNELS" "1 2 4 6 8 16 32" \
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"BITS_PER_SAMPLE" "8 12 16" \
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"BITS_PER_SAMPLE" "8 12 16" \
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"CONVERTER_RESOLUTION" "8 11 12 16" \
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"CONVERTER_RESOLUTION" "8 11 12 16" \
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"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
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"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
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@ -255,8 +255,8 @@ module ad_ip_jesd204_tpl_adc_regmap #(
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genvar i;
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genvar i;
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for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
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for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
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up_adc_channel #(
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up_adc_channel #(
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.COMMON_ID (6'h1),
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.COMMON_ID (6'h1 + i/16),
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.CHANNEL_ID (i),
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.CHANNEL_ID (i % 16),
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.USERPORTS_DISABLE (1),
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.USERPORTS_DISABLE (1),
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.DCFILTER_DISABLE (1),
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.DCFILTER_DISABLE (1),
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.IQCORRECTION_DISABLE (1)
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.IQCORRECTION_DISABLE (1)
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