From 002f8d8a3eb875b1d7a0cb33c48924dceaa7926f Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 15 Nov 2019 13:12:58 +0000 Subject: [PATCH] jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters --- .../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl | 4 ++-- .../ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl index 656e6ac78..5df159492 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl @@ -68,8 +68,8 @@ adi_add_bus "link" "master" \ adi_add_bus_clock "link_clk" "link" foreach {p v} { - "NUM_LANES" "1 2 3 4 8" \ - "NUM_CHANNELS" "1 2 4 6 8" \ + "NUM_LANES" "1 2 3 4 8 16" \ + "NUM_CHANNELS" "1 2 4 6 8 16 32" \ "BITS_PER_SAMPLE" "8 12 16" \ "CONVERTER_RESOLUTION" "8 11 12 16" \ "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v index 09cd10036..0cb15a0fe 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -255,8 +255,8 @@ module ad_ip_jesd204_tpl_adc_regmap #( genvar i; for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel up_adc_channel #( - .COMMON_ID (6'h1), - .CHANNEL_ID (i), + .COMMON_ID (6'h1 + i/16), + .CHANNEL_ID (i % 16), .USERPORTS_DISABLE (1), .DCFILTER_DISABLE (1), .IQCORRECTION_DISABLE (1)