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pluto_hdl_adi/library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc

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axi_xcvrlb- constraints
2016-09-19 17:27:17 +00:00
constraints: Update constraints Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.
2017-02-24 11:43:32 +00:00
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
axi_xcvrlb- constraints
2016-09-19 17:27:17 +00:00
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]