pluto_hdl_adi/library/axi_adc_decimate/axi_adc_decimate.v

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
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//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
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//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adc_decimate(
input adc_clk,
input adc_rst,
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input [15:0] adc_data_a,
input [15:0] adc_data_b,
input adc_valid_a,
input adc_valid_b,
output [15:0] adc_dec_data_a,
output [15:0] adc_dec_data_b,
output adc_dec_valid_a,
output adc_dec_valid_b,
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// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal signals
wire up_clk;
wire up_rstn;
wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [ 4:0] up_raddr;
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wire [31:0] decimation_ratio;
wire [ 2:0] filter_mask;
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// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
axi_adc_decimate_filter axi_adc_decimate_filter (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.decimation_ratio (decimation_ratio),
.filter_mask (filter_mask),
.adc_valid_a(adc_valid_a),
.adc_valid_b(adc_valid_b),
.adc_data_a(adc_data_a[11:0]),
.adc_data_b(adc_data_b[11:0]),
.adc_dec_data_a(adc_dec_data_a),
.adc_dec_data_b(adc_dec_data_b),
.adc_dec_valid_a(adc_dec_valid_a),
.adc_dec_valid_b(adc_dec_valid_b));
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axi_adc_decimate_reg axi_adc_decimate_reg (
.clk (adc_clk),
.adc_decimation_ratio (decimation_ratio),
.adc_filter_mask (filter_mask),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi #(
.AXI_ADDRESS_WIDTH(7),
.ADDRESS_WIDTH(5)
) i_up_axi (
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.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************