298 lines
9.5 KiB
Coq
298 lines
9.5 KiB
Coq
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1)
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`timescale 1ns/100ps
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module axi_ad9963_if #(
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// this parameter controls the buffer type based on the target device.
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parameter DEVICE_TYPE = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface (receive)
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input trx_clk,
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input trx_iq,
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input [11:0] trx_data,
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// physical interface (transmit)
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output tx_clk,
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output tx_iq,
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output [11:0] tx_data,
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// clock (common to both receive and transmit)
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input rst,
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output l_clk,
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output dac_clk,
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// receive data path interface
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output reg adc_valid,
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output reg [23:0] adc_data,
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output reg adc_status,
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// transmit data path interface
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input dac_valid,
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input [23:0] dac_data,
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// delay interface
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input up_clk,
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input [12:0] up_adc_dld,
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input [64:0] up_adc_dwdata,
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output [64:0] up_adc_drdata,
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input [13:0] up_dac_dld,
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input [69:0] up_dac_dwdata,
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output [69:0] up_dac_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal registers
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reg [11:0] rx_data_p = 0;
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reg [11:0] tx_data_p = 'd0;
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reg [11:0] tx_data_n = 'd0;
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reg tx_n_iq = 'd0;
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reg tx_p_iq = 'd0;
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// internal signals
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wire [11:0] rx_data_p_s;
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wire [11:0] rx_data_n_s;
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wire rx_iq_p_s;
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wire rx_iq_n_s;
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wire feedback_clk;
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wire tx_clk_pll;
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genvar l_inst;
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always @(posedge l_clk) begin
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if( rx_iq_p_s == 1'b1) begin
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adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I
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adc_valid <= 1'b1; // data[23:12] Q
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end else begin
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rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge
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adc_data <= {rx_data_p, rx_data_n_s} ; // so we take current N data with previous P data
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adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA
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end
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end
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always @(posedge dac_clk) begin
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if(dac_valid == 1'b1) begin
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tx_data_p <= dac_data[11:0] ;
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tx_data_n <= dac_data[23:12];
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tx_p_iq <= 1'b1;
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tx_n_iq <= 1'b0;
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end
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end
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always @(posedge l_clk) begin
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if (rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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// device clock interface (receive clock)
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BUFG i_clk_gbuf (
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.I (trx_clk),
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.O (l_clk));
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// receive data interface, ibuf -> idelay -> iddr
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_data (
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.rx_clk (l_clk),
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.rx_data_in_p (trx_data[l_inst]),
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.rx_data_in_n (1'b0),
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.rx_data_p (rx_data_p_s[l_inst]),
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.rx_data_n (rx_data_n_s[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[l_inst]),
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.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// receive iq interface, ibuf -> idelay -> iddr
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_iq (
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.rx_clk (l_clk),
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.rx_data_in_p (trx_iq),
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.rx_data_in_n (1'b0),
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.rx_data_p (rx_iq_p_s),
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.rx_data_n (rx_iq_n_s),
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.up_clk (up_clk),
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.up_dld (up_adc_dld[12]),
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.up_dwdata (up_adc_dwdata[64:60]),
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.up_drdata (up_adc_drdata[64:60]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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// transmit data interface, oddr -> obuf
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (1),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_tx_data (
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.tx_clk (dac_clk),
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.tx_data_p (tx_data_p[l_inst]),
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.tx_data_n (tx_data_n[l_inst]),
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.tx_data_out_p (tx_data[l_inst]),
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.tx_data_out_n (),
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.up_clk (up_clk),
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.up_dld (up_dac_dld[l_inst]),
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.up_dwdata (up_dac_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_dac_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// transmit iq interface, oddr -> obuf
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ad_lvds_out #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.SINGLE_ENDED (1),
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.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_tx_iq (
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.tx_clk (dac_clk),
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.tx_data_p (tx_p_iq),
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.tx_data_n (tx_n_iq),
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.tx_data_out_p (tx_iq),
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.tx_data_out_n (),
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.up_clk (up_clk),
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.up_dld (up_dac_dld[12]),
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.up_dwdata (up_dac_dwdata[64:60]),
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.up_drdata (up_dac_drdata[64:60]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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// transmit clock interface, oddr -> obuf
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PLLE2_BASE #(
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.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
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.CLKFBOUT_MULT(15), // Multiply value for all CLKOUT, (2-64)
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.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
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.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
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// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
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.CLKOUT0_DIVIDE(20),
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.CLKOUT1_DIVIDE(20),
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.CLKOUT2_DIVIDE(1),
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.CLKOUT3_DIVIDE(1),
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.CLKOUT4_DIVIDE(1),
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.CLKOUT5_DIVIDE(1),
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// CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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// CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
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.CLKOUT0_PHASE(90.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(1), // Master division value, (1-56)
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.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
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.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
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)
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PLLE2_BASE_inst (
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// Clock Outputs: 1-bit (each) output: User configurable clock outputs
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.CLKOUT0(tx_clk_pll), // 1-bit output: CLKOUT0
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.CLKOUT1(dac_clk), // 1-bit output: CLKOUT1
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.CLKOUT2(), // 1-bit output: CLKOUT2
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.CLKOUT3(), // 1-bit output: CLKOUT3
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.CLKOUT4(), // 1-bit output: CLKOUT4
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.CLKOUT5(), // 1-bit output: CLKOUT5
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// Feedback Clocks: 1-bit (each) output: Clock feedback ports
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.CLKFBOUT(feedback_clk), // 1-bit output: Feedback clock
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.LOCKED(), // 1-bit output: LOCK
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.CLKIN1(l_clk), // 1-bit input: Input clock
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// Control Ports: 1-bit (each) input: PLL control ports
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.PWRDWN(1'b0), // 1-bit input: Power-down
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.RST(rst), // 1-bit input: Reset
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// Feedback Clocks: 1-bit (each) input: Clock feedback ports
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.CLKFBIN(feedback_clk) // 1-bit input: Feedback clock
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);
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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i_tx_clk_oddr(
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (tx_clk_pll),
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.D1 (1'b1),
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.D2 (1'b0),
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.Q (tx_clk));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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