89 lines
4.8 KiB
VHDL
89 lines
4.8 KiB
VHDL
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- SPDIF transmitter component package. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/07/14 17:58:49 gedra
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-- Added new components.
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--
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-- Revision 1.1 2004/07/13 18:30:25 gedra
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-- Transmitter component declarations.
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--
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--
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--
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library ieee;
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use ieee.std_logic_1164.all;
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package tx_package is
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component tx_encoder
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generic
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(
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DATA_WIDTH: integer range 16 to 32 := 32
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);
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port
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(
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up_clk: in std_logic; -- clock
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data_clk : in std_logic; -- data clock
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resetn : in std_logic; -- resetn
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conf_mode: in std_logic_vector(3 downto 0); -- sample format
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conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
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conf_txdata: in std_logic; -- sample data enable
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conf_txen: in std_logic; -- spdif signal enable
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chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
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chstat_gstat: in std_logic; -- generation status
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chstat_preem: in std_logic; -- preemphasis status
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chstat_copy: in std_logic; -- copyright bit
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chstat_audio: in std_logic; -- data format
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sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
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sample_data_ack : out std_logic; -- sample buffer read
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channel: out std_logic;
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spdif_tx_o: out std_logic
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);
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end component;
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end tx_package;
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