331 lines
11 KiB
Coq
331 lines
11 KiB
Coq
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top #(
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// Dummy parameters to workaround critical warning
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parameter SAMPLE_RATE = 250,
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parameter RX_JESD_M = 8,
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parameter RX_JESD_L = 4,
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parameter RX_JESD_S = 1,
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parameter RX_JESD_NP = 16,
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parameter RX_NUM_LINKS = 1,
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parameter TX_JESD_M = 8,
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parameter TX_JESD_L = 4,
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parameter TX_JESD_S = 1,
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parameter TX_JESD_NP = 16,
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parameter TX_NUM_LINKS = 1,
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parameter RX_KS_PER_CHANNEL = 32,
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parameter TX_KS_PER_CHANNEL = 32
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) (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// hps-ddr4 (32)
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input hps_ddr_ref_clk,
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output [ 0:0] hps_ddr_clk_p,
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output [ 0:0] hps_ddr_clk_n,
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output [ 16:0] hps_ddr_a,
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output [ 1:0] hps_ddr_ba,
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output [ 0:0] hps_ddr_bg,
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output [ 0:0] hps_ddr_cke,
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output [ 0:0] hps_ddr_cs_n,
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output [ 0:0] hps_ddr_odt,
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output [ 0:0] hps_ddr_reset_n,
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output [ 0:0] hps_ddr_act_n,
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output [ 0:0] hps_ddr_par,
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input [ 0:0] hps_ddr_alert_n,
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inout [ 3:0] hps_ddr_dqs_p,
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inout [ 3:0] hps_ddr_dqs_n,
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inout [ 31:0] hps_ddr_dq,
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inout [ 3:0] hps_ddr_dbi_n,
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input hps_ddr_rzq,
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// hps-ethernet
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input [ 0:0] hps_eth_rxclk,
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input [ 0:0] hps_eth_rxctl,
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input [ 3:0] hps_eth_rxd,
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output [ 0:0] hps_eth_txclk,
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output [ 0:0] hps_eth_txctl,
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output [ 3:0] hps_eth_txd,
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output [ 0:0] hps_eth_mdc,
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inout [ 0:0] hps_eth_mdio,
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// hps-sdio
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output [ 0:0] hps_sdio_clk,
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inout [ 0:0] hps_sdio_cmd,
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inout [ 7:0] hps_sdio_d,
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// hps-usb
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input [ 0:0] hps_usb_clk,
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input [ 0:0] hps_usb_dir,
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input [ 0:0] hps_usb_nxt,
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output [ 0:0] hps_usb_stp,
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inout [ 7:0] hps_usb_d,
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// hps-uart
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input [ 0:0] hps_uart_rx,
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output [ 0:0] hps_uart_tx,
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// hps-i2c (shared w fmc-a, fmc-b)
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inout [ 0:0] hps_i2c_sda,
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inout [ 0:0] hps_i2c_scl,
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// hps-gpio (max-v-u16)
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inout [ 3:0] hps_gpio,
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// gpio (max-v-u21)
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input [ 7:0] gpio_bd_i,
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output [ 3:0] gpio_bd_o,
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// FMC HPC IOs
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// lane interface
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input clkin6,
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input fpga_refclk_in,
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input [7:0] rx_data,
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output [7:0] tx_data,
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input [1:0] fpga_syncin,
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output [1:0] fpga_syncout,
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input sysref2,
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// spi
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output spi0_csb,
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input spi0_miso,
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output spi0_mosi,
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output spi0_sclk,
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output spi1_csb,
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output spi1_sclk,
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inout spi1_sdio,
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// gpio
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input [1:0] agc0,
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input [1:0] agc1,
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input [1:0] agc2,
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input [1:0] agc3,
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inout [10:0] gpio,
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inout hmc_gpio1,
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output hmc_sync,
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input [1:0] irqb,
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output rstb,
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output [1:0] rxen,
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output [1:0] txen
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);
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// internal signals
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wire sys_hps_resetn;
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wire sys_resetn_s;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 7:0] spi_csn_s;
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wire dac_fifo_bypass;
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// assignments
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assign spi0_csb = spi_csn_s[0];
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assign spi1_csb = spi_csn_s[1];
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assign spi0_sclk = spi_clk;
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assign spi1_sclk = spi_clk;
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assign spi0_mosi = spi_mosi;
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ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_hmc (
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.spi_csn (spi_csn_s[1]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_hmc_miso),
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.spi_sdio (spi1_sdio),
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.spi_dir ());
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assign spi_miso = ~spi_csn_s[0] ? spi0_miso :
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~spi_csn_s[1] ? spi_hmc_miso :
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1'b0;
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// gpio
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// TODO output only for now
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assign hmc_gpio1 = gpio_o[43];
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assign gpio_i[44] = agc0[0];
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assign gpio_i[45] = agc0[1];
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assign gpio_i[46] = agc1[0];
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assign gpio_i[47] = agc1[1];
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assign gpio_i[48] = agc2[0];
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assign gpio_i[49] = agc2[1];
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assign gpio_i[50] = agc3[0];
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assign gpio_i[51] = agc3[1];
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assign gpio_i[52] = irqb[0];
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assign gpio_i[53] = irqb[1];
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assign hmc_sync = gpio_o[54];
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assign rstb = gpio_o[55];
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assign rxen[0] = gpio_o[56];
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assign rxen[1] = gpio_o[57];
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assign txen[0] = gpio_o[58];
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assign txen[1] = gpio_o[59];
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assign dac_fifo_bypass = gpio_o[60];
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// board stuff (max-v-u21)
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assign gpio_i[31:14] = gpio_o[31:14];
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assign gpio_i[13:13] = 1'b1;
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assign gpio_i[12:12] = 1'b0;
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assign gpio_i[11: 4] = gpio_bd_i;
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assign gpio_i[ 3: 0] = gpio_o[3:0];
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assign gpio_bd_o = gpio_o[3:0];
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// Unused GPIOs
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assign gpio_i[63:60] = gpio_o[63:60];
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// peripheral reset
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assign sys_resetn_s = sys_resetn & sys_hps_resetn;
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// instantiations
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system_bd i_system_bd (
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.mxfe_gpio_export (gpio),
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.sys_clk_clk (sys_clk),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_hps_ddr_mem_ck (hps_ddr_clk_p),
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.sys_hps_ddr_mem_ck_n (hps_ddr_clk_n),
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.sys_hps_ddr_mem_a (hps_ddr_a),
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.sys_hps_ddr_mem_act_n (hps_ddr_act_n),
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.sys_hps_ddr_mem_ba (hps_ddr_ba),
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.sys_hps_ddr_mem_bg (hps_ddr_bg),
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.sys_hps_ddr_mem_cke (hps_ddr_cke),
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.sys_hps_ddr_mem_cs_n (hps_ddr_cs_n),
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.sys_hps_ddr_mem_odt (hps_ddr_odt),
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.sys_hps_ddr_mem_reset_n (hps_ddr_reset_n),
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.sys_hps_ddr_mem_par (hps_ddr_par),
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.sys_hps_ddr_mem_alert_n (hps_ddr_alert_n),
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.sys_hps_ddr_mem_dqs (hps_ddr_dqs_p),
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.sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n),
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.sys_hps_ddr_mem_dq (hps_ddr_dq),
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.sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n),
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.sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq),
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.sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk),
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.sys_hps_ddr_rstn_reset_n (sys_resetn),
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.sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk),
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.sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]),
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.sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]),
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.sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]),
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.sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]),
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.sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl),
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.sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl),
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.sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk),
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.sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]),
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.sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]),
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.sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]),
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.sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]),
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.sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio),
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.sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc),
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.sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd),
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.sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]),
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.sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]),
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.sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]),
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.sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]),
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.sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]),
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.sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]),
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.sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]),
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.sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]),
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.sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk),
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.sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]),
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.sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]),
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.sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]),
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.sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]),
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.sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]),
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.sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]),
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.sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]),
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.sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]),
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.sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk),
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.sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp),
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.sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir),
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.sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt),
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.sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx),
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.sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx),
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.sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda),
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.sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl),
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.sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]),
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.sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]),
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.sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]),
|
||
|
|
.sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]),
|
||
|
|
.sys_hps_out_rstn_reset_n (sys_hps_resetn),
|
||
|
|
.sys_hps_rstn_reset_n (sys_resetn),
|
||
|
|
.sys_rstn_reset_n (sys_resetn_s),
|
||
|
|
.pr_rom_data_nc_rom_data('h0),
|
||
|
|
// FMC HPC
|
||
|
|
.sys_spi_MISO (spi_miso),
|
||
|
|
.sys_spi_MOSI (spi_mosi),
|
||
|
|
.sys_spi_SCLK (spi_clk),
|
||
|
|
.sys_spi_SS_n (spi_csn_s),
|
||
|
|
.tx_serial_data_tx_serial_data (tx_data[7:0]),
|
||
|
|
.tx_ref_clk_clk (fpga_refclk_in),
|
||
|
|
.tx_sync_export (fpga_syncin),
|
||
|
|
.tx_sysref_export (sysref2),
|
||
|
|
.tx_device_clk_clk (clkin6),
|
||
|
|
.rx_serial_data_rx_serial_data (rx_data[7:0]),
|
||
|
|
.rx_ref_clk_clk (fpga_refclk_in),
|
||
|
|
.rx_sync_export (fpga_syncout),
|
||
|
|
.rx_sysref_export (sysref2),
|
||
|
|
.rx_device_clk_clk (clkin6),
|
||
|
|
.tx_fifo_bypass_bypass (dac_fifo_bypass)
|
||
|
|
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
// ***************************************************************************
|
||
|
|
// ***************************************************************************
|