2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2017-03-20 16:15:18 +00:00
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2023-07-06 12:08:22 +00:00
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# c5soc carrier qsys
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2017-06-08 19:03:03 +00:00
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set system_type c5soc
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2017-03-20 16:15:18 +00:00
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# system clock
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2017-05-12 17:40:14 +00:00
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add_instance sys_clk clock_source
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value sys_clk {clockFrequency} {50000000.0}
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set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
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set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
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add_interface sys_clk clock sink
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add_interface sys_rst reset sink
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set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
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set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
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# hps
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2017-05-12 17:40:14 +00:00
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add_instance sys_hps altera_hps
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0}
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2022-04-20 09:11:31 +00:00
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set_instance_parameter_value sys_hps {F2SDRAM_Type} {AXI-3 AXI-3 AXI-3}
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value sys_hps {F2SDRAM_Width} {64 64 64}
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set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1}
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set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A}
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set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII}
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set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS}
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set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data}
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set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {USB0_Mode} {N/A}
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set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {USB1_Mode} {SDR}
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set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {SPIM0_Mode} {N/A}
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set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select}
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set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0}
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set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control}
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set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused}
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set_instance_parameter_value sys_hps {UART1_Mode} {N/A}
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2017-06-29 14:26:58 +00:00
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set_instance_parameter_value sys_hps {I2C0_PinMuxing} {FPGA}
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set_instance_parameter_value sys_hps {I2C0_Mode} {Full}
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0}
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set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {1}
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set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0}
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set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0}
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set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {100.0}
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set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3}
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set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0}
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set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0}
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set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3}
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set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0}
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set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32}
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set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15}
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set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10}
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set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3}
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set_instance_parameter_value sys_hps {MEM_TCL} {11}
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set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/7}
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set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/4}
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set_instance_parameter_value sys_hps {MEM_WTCL} {8}
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set_instance_parameter_value sys_hps {MEM_RTT_WR} {RZQ/4}
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set_instance_parameter_value sys_hps {TIMING_TIS} {180}
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set_instance_parameter_value sys_hps {TIMING_TIH} {140}
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set_instance_parameter_value sys_hps {TIMING_TDS} {30}
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set_instance_parameter_value sys_hps {TIMING_TDH} {65}
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set_instance_parameter_value sys_hps {TIMING_TDQSQ} {125}
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set_instance_parameter_value sys_hps {TIMING_TQH} {0.38}
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set_instance_parameter_value sys_hps {TIMING_TDQSCK} {255}
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set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25}
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set_instance_parameter_value sys_hps {TIMING_TQSH} {0.4}
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set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2}
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set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2}
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set_instance_parameter_value sys_hps {MEM_TINIT_US} {500}
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set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4}
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set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0}
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set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75}
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set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75}
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set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8}
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set_instance_parameter_value sys_hps {MEM_TRFC_NS} {260.0}
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set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0}
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set_instance_parameter_value sys_hps {MEM_TWTR} {4}
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set_instance_parameter_value sys_hps {MEM_TFAW_NS} {30.0}
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set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5}
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set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5}
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set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.03}
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set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.02}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {0.09}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.16}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.01}
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set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.08}
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set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0}
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set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.03}
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set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0}
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add_interface sys_hps_memory conduit end
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set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory
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add_interface sys_hps_hps_io conduit end
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set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io
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add_interface sys_hps_h2f_reset reset source
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set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset
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add_connection sys_clk.clk sys_hps.f2h_sdram0_clock
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add_connection sys_clk.clk sys_hps.h2f_axi_clock
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add_connection sys_clk.clk sys_hps.f2h_axi_clock
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add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock
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2017-06-29 14:26:58 +00:00
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add_interface sys_hps_i2c0 conduit end
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set_interface_property sys_hps_i2c0 EXPORT_OF sys_hps.i2c0
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add_interface sys_hps_i2c0_clk clock source
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set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
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add_interface sys_hps_i2c0_scl_in clock sink
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set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
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2017-03-20 16:15:18 +00:00
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# cpu/hps handling
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proc ad_cpu_interrupt {m_irq m_port} {
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add_connection sys_hps.f2h_irq0 ${m_port}
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2017-03-20 19:42:33 +00:00
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set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
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2017-03-20 16:15:18 +00:00
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}
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proc ad_cpu_interconnect {m_base m_port} {
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add_connection sys_hps.h2f_lw_axi_master ${m_port}
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set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
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}
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proc ad_dma_interconnect {m_port m_id} {
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2022-04-20 09:11:31 +00:00
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if {${m_id} == 0} {
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add_connection ${m_port} sys_hps.f2h_sdram0_data
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set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram0_data baseAddress {0x0000}
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return
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}
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2017-03-20 19:42:33 +00:00
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if {${m_id} == 1} {
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2017-03-20 16:15:18 +00:00
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add_connection ${m_port} sys_hps.f2h_sdram1_data
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set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
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2017-03-20 19:42:33 +00:00
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return
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2017-03-20 16:15:18 +00:00
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}
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add_connection ${m_port} sys_hps.f2h_sdram2_data
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set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram2_data baseAddress {0x0000}
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}
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# common dma interfaces
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2017-05-12 17:40:14 +00:00
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add_instance sys_dma_clk clock_source
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2017-03-20 16:15:18 +00:00
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add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
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add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
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add_connection sys_dma_clk.clk sys_hps.f2h_sdram1_clock
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add_connection sys_dma_clk.clk sys_hps.f2h_sdram2_clock
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# internal memory
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2017-05-12 17:40:14 +00:00
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add_instance sys_int_mem altera_avalon_onchip_memory2
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2017-03-20 16:15:18 +00:00
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set_instance_parameter_value sys_int_mem {dualPort} {0}
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set_instance_parameter_value sys_int_mem {dataWidth} {64}
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set_instance_parameter_value sys_int_mem {memorySize} {65536.0}
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set_instance_parameter_value sys_int_mem {initMemContent} {0}
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add_connection sys_clk.clk sys_int_mem.clk1
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add_connection sys_clk.clk_reset sys_int_mem.reset1
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add_connection sys_hps.h2f_axi_master sys_int_mem.s1
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set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000}
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2022-04-20 09:11:31 +00:00
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# display (vga-out)
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add_instance vga_out axi_hdmi_tx
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set_instance_parameter_value vga_out {CR_CB_N} {0}
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set_instance_parameter_value vga_out {INTERFACE} {VGA_INTERFACE}
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set_instance_parameter_value vga_out {ID} {0}
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add_interface vga_out_vga_if conduit end
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set_interface_property vga_out_vga_if EXPORT_OF vga_out.vga_if
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add_connection sys_clk.clk vga_out.s_axi_clock
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add_connection sys_clk.clk_reset vga_out.s_axi_reset
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# display (pixel-clk-pll)
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add_instance pixel_clk_pll altera_pll
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set_instance_parameter_value pixel_clk_pll {gui_device_speed_grade} {2}
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set_instance_parameter_value pixel_clk_pll {gui_reference_clock_frequency} {50.0}
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set_instance_parameter_value pixel_clk_pll {gui_use_locked} {0}
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set_instance_parameter_value pixel_clk_pll {gui_number_of_clocks} {2}
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set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency0} {65.00}
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set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency1} {100.0}
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set_instance_parameter_value pixel_clk_pll {gui_en_reconf} {1}
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add_connection sys_clk.clk pixel_clk_pll.refclk
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add_connection sys_clk.clk_reset pixel_clk_pll.reset
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add_connection pixel_clk_pll.outclk1 sys_hps.f2h_sdram0_clock
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add_connection pixel_clk_pll.outclk1 vga_out.vdma_clock
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add_connection pixel_clk_pll.outclk0 vga_out.reference_clk
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# display (pixel-clk-pll-reconfig)
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add_instance pixel_clk_pll_reconfig altera_pll_reconfig
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set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_BYTEENABLE} {0}
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set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_MIF} {0}
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add_connection pixel_clk_pll.reconfig_from_pll pixel_clk_pll_reconfig.reconfig_from_pll
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set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPortLSB {0}
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set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPortLSB {0}
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set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll width {0}
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add_connection pixel_clk_pll.reconfig_to_pll pixel_clk_pll_reconfig.reconfig_to_pll
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set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPortLSB {0}
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set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
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set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll width {0}
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add_connection sys_clk.clk pixel_clk_pll_reconfig.mgmt_clk
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add_connection sys_clk.clk_reset pixel_clk_pll_reconfig.mgmt_reset
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#display (video-dmac)
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add_instance video_dmac axi_dmac
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set_instance_parameter_value video_dmac {AUTO_ASYNC_CLK} {1}
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set_instance_parameter_value video_dmac {AXI_SLICE_DEST} {0}
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set_instance_parameter_value video_dmac {AXI_SLICE_SRC} {0}
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set_instance_parameter_value video_dmac {CYCLIC} {1}
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set_instance_parameter_value video_dmac {HAS_AXIS_TLAST} {1}
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set_instance_parameter_value video_dmac {DMA_2D_TRANSFER} {1}
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set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_DEST} {64}
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set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_SRC} {64}
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set_instance_parameter_value video_dmac {DMA_LENGTH_WIDTH} {24}
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set_instance_parameter_value video_dmac {DMA_TYPE_DEST} {1}
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set_instance_parameter_value video_dmac {DMA_TYPE_SRC} {0}
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set_instance_parameter_value video_dmac {FIFO_SIZE} {8}
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set_instance_parameter_value video_dmac {ID} {0}
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set_instance_parameter_value video_dmac {SYNC_TRANSFER_START} {0}
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add_connection video_dmac.m_axis vga_out.vdma_if axi4stream
|
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add_connection pixel_clk_pll.outclk1 video_dmac.m_src_axi_clock
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add_connection pixel_clk_pll.outclk1 video_dmac.if_m_axis_aclk
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add_connection sys_clk.clk video_dmac.s_axi_clock
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add_connection sys_clk.clk_reset video_dmac.m_src_axi_reset
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add_connection sys_clk.clk_reset video_dmac.s_axi_reset
|
2017-03-20 16:15:18 +00:00
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# id
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2017-05-12 17:40:14 +00:00
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add_instance sys_id altera_avalon_sysid_qsys
|
2017-03-20 16:15:18 +00:00
|
|
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set_instance_parameter_value sys_id {id} {-1395322110}
|
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|
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add_connection sys_clk.clk sys_id.clk
|
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add_connection sys_clk.clk_reset sys_id.reset
|
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|
|
# gpio-bd
|
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|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance sys_gpio_bd altera_avalon_pio
|
2017-03-20 16:15:18 +00:00
|
|
|
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
|
|
|
|
|
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
|
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|
|
set_instance_parameter_value sys_gpio_bd {width} {32}
|
|
|
|
|
add_connection sys_clk.clk sys_gpio_bd.clk
|
|
|
|
|
add_connection sys_clk.clk_reset sys_gpio_bd.reset
|
|
|
|
|
add_interface sys_gpio_bd conduit end
|
2017-03-20 19:42:33 +00:00
|
|
|
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
|
2017-03-20 16:15:18 +00:00
|
|
|
|
|
|
|
|
# gpio-in
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance sys_gpio_in altera_avalon_pio
|
2017-03-20 16:15:18 +00:00
|
|
|
set_instance_parameter_value sys_gpio_in {direction} {Input}
|
|
|
|
|
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
|
|
|
|
|
set_instance_parameter_value sys_gpio_in {width} {32}
|
|
|
|
|
add_connection sys_clk.clk_reset sys_gpio_in.reset
|
|
|
|
|
add_connection sys_clk.clk sys_gpio_in.clk
|
|
|
|
|
add_interface sys_gpio_in conduit end
|
|
|
|
|
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
|
|
|
|
|
|
|
|
|
|
# gpio-out
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance sys_gpio_out altera_avalon_pio
|
2017-03-20 16:15:18 +00:00
|
|
|
set_instance_parameter_value sys_gpio_out {direction} {Output}
|
|
|
|
|
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
|
|
|
|
|
set_instance_parameter_value sys_gpio_out {width} {32}
|
|
|
|
|
add_connection sys_clk.clk_reset sys_gpio_out.reset
|
|
|
|
|
add_connection sys_clk.clk sys_gpio_out.clk
|
|
|
|
|
add_interface sys_gpio_out conduit end
|
|
|
|
|
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
|
|
|
|
|
|
|
|
|
|
# spi
|
|
|
|
|
|
2017-05-12 17:40:14 +00:00
|
|
|
add_instance sys_spi altera_avalon_spi
|
2017-03-20 16:15:18 +00:00
|
|
|
set_instance_parameter_value sys_spi {clockPhase} {0}
|
|
|
|
|
set_instance_parameter_value sys_spi {clockPolarity} {1}
|
|
|
|
|
set_instance_parameter_value sys_spi {dataWidth} {8}
|
|
|
|
|
set_instance_parameter_value sys_spi {masterSPI} {1}
|
|
|
|
|
set_instance_parameter_value sys_spi {numberOfSlaves} {1}
|
|
|
|
|
set_instance_parameter_value sys_spi {targetClockRate} {50000000.0}
|
|
|
|
|
add_connection sys_clk.clk sys_spi.clk
|
|
|
|
|
add_connection sys_clk.clk_reset sys_spi.reset
|
|
|
|
|
add_interface sys_spi conduit end
|
|
|
|
|
set_interface_property sys_spi EXPORT_OF sys_spi.external
|
|
|
|
|
|
2020-08-18 20:52:39 +00:00
|
|
|
# system id
|
|
|
|
|
|
|
|
|
|
add_instance axi_sysid_0 axi_sysid
|
|
|
|
|
add_instance rom_sys_0 sysid_rom
|
|
|
|
|
add_connection axi_sysid_0.if_rom_addr rom_sys_0.if_rom_addr
|
|
|
|
|
add_connection rom_sys_0.if_rom_data axi_sysid_0.if_sys_rom_data
|
|
|
|
|
add_connection sys_clk.clk rom_sys_0.if_clk
|
|
|
|
|
add_connection sys_clk.clk axi_sysid_0.s_axi_clock
|
|
|
|
|
add_connection sys_clk.clk_reset axi_sysid_0.s_axi_reset
|
|
|
|
|
add_interface pr_rom_data_nc conduit end
|
|
|
|
|
set_interface_property pr_rom_data_nc EXPORT_OF axi_sysid_0.if_pr_rom_data
|
|
|
|
|
|
2017-03-20 16:15:18 +00:00
|
|
|
# interrupts
|
|
|
|
|
|
|
|
|
|
ad_cpu_interrupt 0 sys_gpio_bd.irq
|
|
|
|
|
ad_cpu_interrupt 1 sys_spi.irq
|
2022-04-20 09:11:31 +00:00
|
|
|
ad_cpu_interrupt 4 video_dmac.interrupt_sender
|
2017-03-20 16:15:18 +00:00
|
|
|
|
|
|
|
|
# cpu interconnects
|
|
|
|
|
|
|
|
|
|
ad_cpu_interconnect 0x00108000 sys_spi.spi_control_port
|
|
|
|
|
ad_cpu_interconnect 0x00010000 sys_id.control_slave
|
|
|
|
|
ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1
|
|
|
|
|
ad_cpu_interconnect 0x00010100 sys_gpio_in.s1
|
|
|
|
|
ad_cpu_interconnect 0x00109000 sys_gpio_out.s1
|
2020-08-18 20:52:39 +00:00
|
|
|
ad_cpu_interconnect 0x00018000 axi_sysid_0.s_axi
|
2022-04-20 09:11:31 +00:00
|
|
|
ad_cpu_interconnect 0x00110800 video_dmac.s_axi
|
|
|
|
|
ad_cpu_interconnect 0x00130000 vga_out.s_axi
|
|
|
|
|
ad_cpu_interconnect 0x00118900 pixel_clk_pll_reconfig.mgmt_avalon_slave
|
|
|
|
|
|
|
|
|
|
# mem interconnects
|
|
|
|
|
|
|
|
|
|
ad_dma_interconnect video_dmac.m_src_axi 0
|
|
|
|
|
|
|
|
|
|
|
