2016-05-20 15:46:25 +00:00
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2017-03-01 20:34:04 +00:00
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# qsys- automatically infers these clocks
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2016-05-20 15:46:25 +00:00
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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2016-05-20 20:14:57 +00:00
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create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
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create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
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2017-03-01 20:34:04 +00:00
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create_clock -period "7.503 ns" -name hps_ddr_ref_clk_133mhz [get_ports {hps_ddr_ref_clk}]
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2017-05-01 13:34:45 +00:00
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create_clock -period "7.503 ns" -name sys_ddr_ref_clk_133mhz [get_ports {sys_ddr_ref_clk}]
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2016-05-20 15:46:25 +00:00
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derive_pll_clocks
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derive_clock_uncertainty
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2017-03-01 20:34:04 +00:00
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set_false_path -to [get_registers *sys_gpio_in|readdata[12]*]
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set_false_path -to [get_registers *sys_gpio_in|readdata[13]*]
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2016-06-02 20:22:40 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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2016-11-04 16:20:46 +00:00
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
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2016-06-02 20:22:40 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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2016-11-04 16:20:46 +00:00
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-to [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]
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2016-06-02 20:22:40 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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2016-11-04 16:20:46 +00:00
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-to [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]
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2016-06-02 20:22:40 +00:00
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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2016-11-04 16:20:46 +00:00
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-to [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]
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2016-06-02 20:22:40 +00:00
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2016-11-04 16:20:46 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
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2016-06-02 20:22:40 +00:00
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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2016-11-04 16:20:46 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_tx_xcvr|alt_core_pll|outclk0}]\
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2016-06-02 20:22:40 +00:00
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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2016-11-04 16:20:46 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_xcvr|alt_core_pll|outclk0}]\
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2016-06-02 20:22:40 +00:00
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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2016-11-04 16:20:46 +00:00
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set_false_path -from [get_clocks {i_system_bd|avl_ad9371_rx_os_xcvr|alt_core_pll|outclk0}]\
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2016-06-02 20:22:40 +00:00
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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2017-03-23 13:44:18 +00:00
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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