2023-07-06 12:08:22 +00:00
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###############################################################################
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## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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2017-07-12 09:12:30 +00:00
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package require -exact qsys 13.0
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2022-07-12 11:06:15 +00:00
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source ../../../scripts/adi_env.tcl
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2019-04-01 09:41:00 +00:00
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source ../../scripts/adi_ip_intel.tcl
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2017-07-12 09:12:30 +00:00
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set_module_property NAME util_clkdiv
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set_module_property DESCRIPTION "Clock Division Utility"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME util_clkdiv
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
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2019-04-01 09:41:00 +00:00
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set_fileset_property quartus_synth TOP_LEVEL util_clkdiv
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add_fileset_file util_clkdiv.v VERILOG PATH util_clkdiv.v TOP_LEVEL_FILE
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2017-07-12 09:12:30 +00:00
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# defaults
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2018-08-14 13:53:45 +00:00
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ad_interface clock clk input 1
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ad_interface reset reset input 1 if_clk
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ad_interface clock clk_out output 1
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ad_interface reset reset_out output 1 if_clk_out
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2017-07-12 09:12:30 +00:00
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