pluto_hdl_adi/projects/daq2/vc707/system_bd.tcl


## FIFO depth is 8Mb - 500k samples
set adc_fifo_name axi_ad9680_fifo
set adc_fifo_address_width 17
set adc_data_width 128
set adc_dma_data_width 64

## FIFO depth is 8Mb - 500k samples
set dac_fifo_name axi_ad9144_fifo
set dac_fifo_address_width 16
set dac_data_width 128
set dac_dma_data_width 128

## NOTE: With this configuration the #36Kb BRAM utilization is at ~68.45%

source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source ../common/daq2_bd.tcl
daq2: Initial check in of the VC707 based project NOTE: Can not communicate with the clock chip, rx/tx PLL not locking. 2015-01-28 14:24:06 +00:00
adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`## FIFO depth is 8Mb - 500k samples`
projects/system_bd- adc/dac fifo board designs 2017-02-27 21:05:21 +00:00			`set adc_fifo_name axi_ad9680_fifo`
adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`set adc_fifo_address_width 17`
projects/system_bd- adc/dac fifo board designs 2017-02-27 21:05:21 +00:00			`set adc_data_width 128`
			`set adc_dma_data_width 64`

adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`## FIFO depth is 8Mb - 500k samples`
projects/system_bd- adc/dac fifo board designs 2017-02-27 21:05:21 +00:00			`set dac_fifo_name axi_ad9144_fifo`
adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`set dac_fifo_address_width 16`
projects/system_bd- adc/dac fifo board designs 2017-02-27 21:05:21 +00:00			`set dac_data_width 128`
			`set dac_dma_data_width 128`

adc\|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs The affected projects are: - FMCADC2/VC707 - 16Mb - FMCADC5/VC707 - 16Mb - DAQ2/ZC706 - ADC@1GB and DAC@8Mb - DAQ2/KC705 - ADC@4Mb and DAC@4Mb - DAQ2/VC707 - ADC@8Mb and DAC@8Mb - DAQ2/KCU105 - ADC@4Mb and DAC@4Mb - DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb - DAQ3/ZC706 - ADC@1GB and DAC@8Mb - DAQ3/KCU105 - ADC@4Mb and DAC@4Mb - DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb - ADRV9371x/KCU105 - DAC@8Mb - ADRV9371x/ZCU102 - DAC@16Mb 2018-08-10 07:34:45 +00:00			`## NOTE: With this configuration the #36Kb BRAM utilization is at ~68.45%`

daq2: Initial check in of the VC707 based project NOTE: Can not communicate with the clock chip, rx/tx PLL not locking. 2015-01-28 14:24:06 +00:00			`source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl`
file renamed; sed output; fingers crossed 2017-02-22 20:56:37 +00:00			`source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl`
			`source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl`
daq2: Initial check in of the VC707 based project NOTE: Can not communicate with the clock chip, rx/tx PLL not locking. 2015-01-28 14:24:06 +00:00			`source ../common/daq2_bd.tcl`