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pluto_hdl_adi/library/intel/adi_jesd204/adi_jesd204_hw.tcl

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library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact jesd204-licensing@analog.com for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
package require qsys
source ../../scripts/adi_env.tcl
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2018-08-14 10:08:06 +00:00
source ../../scripts/adi_ip_intel.tcl
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
set version 19.1
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
#
# Wrapper module that instantiates and connects all the components required to
# for a JESD204 link.
#
# The following components are created:
# * Transceiver for each lane
# * Transceiver lane PLL (TX only)
# * Transceiver reset controller
# * Link PLL
# * JESD204 link layer processing
# * JESD204 link layer processing control interface
# * axi_adxcvr link management peripheral
#
ad_ip_create adi_jesd204 {Analog Devices JESD204}
set_module_property VALIDATION_CALLBACK jesd204_validate
set_module_property COMPOSITION_CALLBACK jesd204_compose
# parameters
ad_ip_parameter DEVICE_FAMILY STRING "" false {
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
VISIBLE true
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
}
ad_ip_parameter DEVICE STRING "" false {
SYSTEM_INFO DEVICE
VISIBLE false
}
ad_ip_parameter TX_OR_RX_N BOOLEAN 0 false { \
DISPLAY_HINT "radio" \
DISPLAY_NAME "Data Path" \
ALLOWED_RANGES { "0:Receive" "1:Transmit" }
}
ad_ip_parameter ID NATURAL 0 false { \
DISPLAY_NAME "Core ID" \
}
ad_ip_parameter LANE_RATE FLOAT 10000 false { \
DISPLAY_NAME "Lane Rate" \
DISPLAY_UNITS "Mbps" \
}
ad_ip_parameter SYSCLK_FREQUENCY FLOAT 100.0 false { \
DISPLAY_NAME "System Clock Frequency" \
UNITS Megahertz
}
ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false { \
DISPLAY_NAME "Reference Clock Frequency" \
UNITS Megahertz \
}
ad_ip_parameter NUM_OF_LANES POSITIVE 4 false { \
DISPLAY_NAME "Number of Lanes" \
ALLOWED_RANGES 1:8
}
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN 0 false { \
DISPLAY_HINT "Clock Network" \
DISPLAY_NAME "Clock Network" \
ALLOWED_RANGES { "0:x1/xN (Non-bonded)" "1:x6/xN (Bonded)" }
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
ad_ip_parameter LANE_MAP STRING "" false { \
DISPLAY_NAME "Lane Mapping" \
}
altera: jesd204: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the adi_jesd204 and jesd204_phy for Altera modules. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded depending on whether soft or hard PCS is used to either the soft PCS module or the transceiver block itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-19 14:51:56 +00:00
ad_ip_parameter LANE_INVERT STD_LOGIC_VECTOR 0 false { \
DISPLAY_NAME "Lane Invert Mask" \
DISPLAY_HINT "hexadecimal" \
WIDTH 8 \
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
ad_ip_parameter SOFT_PCS BOOLEAN true false { \
DISPLAY_NAME "Enable Soft PCS" \
}
intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS
2020-04-21 13:38:36 +00:00
ad_ip_parameter INPUT_PIPELINE_STAGES INTEGER 0 false { \
intel/adi_jesd204: Expose REGISTER_INPUTS parameter Define INPUT_PIPELINE parameter, which can be used to activate the REGISTER_INPUTS parameter of the PHY. This parameter will add an additional register stage into the incoming parallel data stream. It can be used to relax the timing margin between the PHY and Link modules.
2020-02-05 14:26:21 +00:00
DISPLAY_NAME "Enable input pipeline" \
}
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \
intel/adi_jesd204: Expose REGISTER_INPUTS parameter Define INPUT_PIPELINE parameter, which can be used to activate the REGISTER_INPUTS parameter of the PHY. This parameter will add an additional register stage into the incoming parallel data stream. It can be used to relax the timing margin between the PHY and Link modules.
2020-02-05 14:26:21 +00:00
DISPLAY_NAME "External Device Clock Enable" \
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
}
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 false { \
DISPLAY_NAME "Transport layer datapath width" \
DISPLAY_UNITS "octets" \
ALLOWED_RANGES {4 6 8 12} \
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} {
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
global version
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set device [get_parameter_value DEVICE_FAMILY]
if {[string equal $device "Arria 10"]} {
add_instance phy_reset_control altera_xcvr_reset_control $version
set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true
set_instance_parameter_value phy_reset_control {SYNCHRONIZE_RESET} {0}
set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
set_instance_parameter_value phy_reset_control {TX_PLL_ENABLE} $tx
set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
add_connection sys_clock.clk phy_reset_control.clock
add_connection link_reset.out_reset phy_reset_control.reset
add_connection sys_clock.clk_reset phy_reset_control.reset
if {$tx} {
set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000}
set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {70000}
set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {70000}
add_connection phy_reset_control.tx_ready axi_xcvr.ready
} else {
set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {70000}
set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {4000}
add_connection phy_reset_control.rx_ready axi_xcvr.ready
}
} elseif {[string equal $device "Stratix 10"]} {
add_instance phy_reset_control altera_xcvr_reset_control_s10 $version
set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes
set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx
set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx]
set_instance_parameter_value phy_reset_control {REDUCED_SIM_TIME} {1}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000}
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set_instance_parameter_value phy_reset_control {T_PLL_LOCK_HYST} {1000}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
add_connection sys_clock.clk phy_reset_control.clock
add_connection link_reset.out_reset phy_reset_control.reset
add_connection sys_clock.clk_reset phy_reset_control.reset
if {$tx} {
set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1}
set_instance_parameter_value phy_reset_control {TX_MANUAL_RESET} {0}
set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {0}
set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {20}
add_connection phy_reset_control.tx_ready axi_xcvr.ready
} else {
set_instance_parameter_value phy_reset_control {RX_MANUAL_RESET} {0}
set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {40}
set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {5000}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
add_connection phy_reset_control.rx_ready axi_xcvr.ready
}
} else {
send_message error "Only Arria 10 and Stratix 10 are supported."
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
}
}
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} {
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
global version
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set device_family [get_parameter_value "DEVICE_FAMILY"]
if {$device_family == "Arria 10"} {
add_instance lane_pll altera_xcvr_atx_pll_a10 $version
if {$num_lanes > 6} {
set_instance_parameter_value lane_pll enable_mcgb {true}
if {$bonding_clocks_en} {
set_instance_parameter_value lane_pll {enable_bonding_clks} {true}
set_instance_parameter_value lane_pll {mcgb_div} {1}
set_instance_parameter_value lane_pll {set_ref_clk_div} {1}
set_instance_parameter_value lane_pll {pma_width} {40}
} else {
set_instance_parameter_value lane_pll enable_hfreq_clk {true}
}
add_instance glue adi_jesd204_glue 1.0
add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown
add_connection glue.out_pll_powerdown lane_pll.pll_powerdown
add_connection glue.out_mcgb_rst lane_pll.mcgb_rst
} else {
add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown
}
set_instance_parameter_value lane_pll {enable_pll_reconfig} {1}
} elseif {$device_family == "Stratix 10"} {
add_instance lane_pll altera_xcvr_atx_pll_s10_htile $version
set_instance_parameter_value lane_pll {rcfg_enable} {1}
## tie pll_select to GND
add_instance glue adi_jesd204_glue 1.0
set_instance_parameter_value glue {IN_PLL_POWERDOWN_EN} {0}
if {$tx_or_rx_n} {
add_connection glue.out_pll_select_gnd phy_reset_control.pll_select
}
} else {
send_message error "Only Arria 10 and Stratix 10 are supported."
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1}
set_instance_parameter_value lane_pll {set_capability_reg_enable} {1}
set_instance_parameter_value lane_pll {set_user_identifier} $id
set_instance_parameter_value lane_pll {set_csr_soft_logic_enable} {1}
set_instance_parameter_value lane_pll {set_output_clock_frequency} $pllclk_frequency
set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $refclk_frequency
altera: adi_jesd204: Add support for more than 6 transmit lanes On Arria10 there are 6 transceivers in a single bank. If more than 6 transceivers are used these will end up in multiple banks. The ATX PLL can directly connect to the transceivers in the same bank through the 1x clock network. To connect to transceivers in another bank it has to go through a master clock generation block (MCGB) and the xN clock network. Add support for instantiating the MCGB if more than 6 lanes are used. In this case the first 6 transceivers will still have a direct connection to the PLL while all other transceivers will be clocked by the MCGB. Note that this requires that the first 6 transceivers are all in the same bank. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-19 14:51:12 +00:00
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
add_connection lane_pll.pll_locked phy_reset_control.pll_locked
add_connection lane_pll.pll_cal_busy phy_reset_control.pll_cal_busy
add_connection ref_clock.out_clk lane_pll.pll_refclk0
add_connection sys_clock.clk lane_pll.reconfig_clk0
add_connection sys_clock.clk_reset lane_pll.reconfig_reset0
add_interface lane_pll_reconfig avalon slave
set_interface_property lane_pll_reconfig EXPORT_OF lane_pll.reconfig_avmm0
}
proc jesd204_get_max_lane_rate {device soft_pcs} {
if {[string range $device 0 2] == "10A"} {
set device_speedgrade [string range $device 13 13]
set pma_speedgrade [string range $device 8 8]
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
} elseif {[string range $device 0 1] == "1S"} {
set device_speedgrade [string range $device 13 13]
set pma_speedgrade [string range $device 8 8]
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
} else {
# Assume fastest speed grade
set device_speedgrade 1
set pma_speedgrade 1
}
if {$soft_pcs} {
if {$pma_speedgrade == 1 || $pma_speedgrade == 2} {
return "15000"
} elseif {$pma_speedgrade == 3} {
return "14200"
} else {
return "12500"
}
} else {
if {$device_speedgrade == 1} {
return "12000"
} elseif {$device_speedgrade == 2} {
return "9830"
} else {
return "8936"
}
}
}
proc jesd204_validate {{quiet false}} {
set soft_pcs [get_parameter_value "SOFT_PCS"]
intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS
2020-04-21 13:38:36 +00:00
set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set device_family [get_parameter_value "DEVICE_FAMILY"]
set device [get_parameter_value "DEVICE"]
set lane_rate [get_parameter_value "LANE_RATE"]
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
if {$device_family != "Arria 10" && $device_family != "Stratix 10"} {
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
if {!$quiet} {
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
send_message error "Only Arria 10 and Startix 10 are supported."
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
}
return false
}
set max_lane_rate [jesd204_get_max_lane_rate $device $soft_pcs]
if {$lane_rate < 2000 || $lane_rate > $max_lane_rate} {
if {!$quiet} {
send_message error "Lane rate must be in the range 2000-${max_lane_rate} Mbps."
if {!$soft_pcs} {
send_message error "Consider enabling soft PCS for a higher maximum lane rate."
intel/adi_jesd204: Expose REGISTER_INPUTS parameter Define INPUT_PIPELINE parameter, which can be used to activate the REGISTER_INPUTS parameter of the PHY. This parameter will add an additional register stage into the incoming parallel data stream. It can be used to relax the timing margin between the PHY and Link modules.
2020-02-05 14:26:21 +00:00
if {$input_pipeline} {
send_message error "Input pipeline can be active just when soft PCS is used."
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
}
}
return false
}
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
set_parameter_property BONDING_CLOCKS_EN VISIBLE [expr ($num_of_lanes > 6) && ($tx_or_rx_n)]
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
return true
}
proc jesd204_compose {} {
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
global version
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set id [get_parameter_value "ID"]
set lane_rate [get_parameter_value "LANE_RATE"]
set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"]
set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
set sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"]
set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
set lane_map [get_parameter_value "LANE_MAP"]
altera: jesd204: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the adi_jesd204 and jesd204_phy for Altera modules. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded depending on whether soft or hard PCS is used to either the soft PCS module or the transceiver block itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-19 14:51:56 +00:00
set lane_invert [get_parameter_value "LANE_INVERT"]
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set soft_pcs [get_parameter_value "SOFT_PCS"]
set device_family [get_parameter_value "DEVICE_FAMILY"]
set device [get_parameter_value "DEVICE"]
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
set ext_device_clk_en [get_parameter_value "EXT_DEVICE_CLK_EN"]
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"]
intel/adi_jesd204: Add an additional pipeline stage to RX soft PCS
2020-04-21 13:38:36 +00:00
set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"]
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set tpl_data_path_width [get_parameter_value "TPL_DATA_PATH_WIDTH"]
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set pllclk_frequency [expr $lane_rate / 2]
set linkclk_frequency [expr $lane_rate / 40]
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set deviceclk_frequency [expr $linkclk_frequency * 4 / $tpl_data_path_width]
set dual_clk_mode [expr $tpl_data_path_width > 4]
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
if {![jesd204_validate true]} {
return
}
intel/jesd204: clock_source instance version is 19.3
2021-01-05 08:59:26 +00:00
add_instance sys_clock clock_source 19.3
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000]
set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert}
add_interface sys_clk clock sink
set_interface_property sys_clk EXPORT_OF sys_clock.clk_in
add_interface sys_resetn reset sink
set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance ref_clock altera_clock_bridge $version
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000]
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set_instance_parameter_value ref_clock {NUM_CLOCK_OUTPUTS} 2
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
add_interface ref_clk clock sink
set_interface_property ref_clk EXPORT_OF ref_clock.in_clk
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set outclk_name ""
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
## link clock configuration (also known as device clock, which will be used
## by the upper layers for the data path, it can come from the PCS or external)
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance link_clock altera_clock_bridge $version
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000]
set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance link_reset altera_reset_bridge $version
altera: adi_jesd204: Export link domain reset Export the reset signal for the link clock domain. This can be used by external logic that is in the link clock domain to reset itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 10:50:45 +00:00
set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
if {$dual_clk_mode} {
if {$ext_device_clk_en} {
set link_clock link_clock.out_clk
set device_clock ext_device_clock.out_clk
set device_clock_export ext_device_clock.out_clk_1
} else {
set link_clock link_clock.out_clk
set device_clock ref_clock.out_clk
set device_clock_export ref_clock.out_clk_1
}
} else {
if {$ext_device_clk_en} {
set link_clock ext_device_clock.out_clk
set device_clock ext_device_clock.out_clk
set device_clock_export ext_device_clock.out_clk_1
} else {
set link_clock link_clock.out_clk
set device_clock link_clock.out_clk
set device_clock_export link_clock.out_clk_1
}
}
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
if {$device_family == "Arria 10"} {
add_instance link_pll altera_xcvr_fpll_a10 $version
set_instance_parameter_value link_pll {gui_fpll_mode} {0}
set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency
adi_jesd204: Configure fPLL phase aligned mode In phase aligned mode the fPLL uses an external feedback path to better align the phase of the PLL output to the phase of the external reference clock. This mode is required for deterministic latency to be able to sample SYSREF which is source synchronous to the external reference clock signal. So far phase aligned mode had been disabled since manual PLL calibration would fail in this mode under certain (unknown) circumstances and dynamic reconfiguration of the PLL would not work. The latest Intel Arria 10 transceiver datasheet contains instructions for the proper calibration sequence to make it work when the PLL is configured for phase aligned mode. Software has been updated accordingly, so enable phase aligned mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-06 11:33:48 +00:00
set_instance_parameter_value link_pll {gui_number_of_output_clocks} 2
set_instance_parameter_value link_pll {gui_enable_phase_alignment} 1
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set_instance_parameter_value link_pll {gui_desired_outclk0_frequency} $linkclk_frequency
set_instance_parameter_value link_pll {enable_pll_reconfig} {1}
adi_jesd204: Configure fPLL phase aligned mode In phase aligned mode the fPLL uses an external feedback path to better align the phase of the PLL output to the phase of the external reference clock. This mode is required for deterministic latency to be able to sample SYSREF which is source synchronous to the external reference clock signal. So far phase aligned mode had been disabled since manual PLL calibration would fail in this mode under certain (unknown) circumstances and dynamic reconfiguration of the PLL would not work. The latest Intel Arria 10 transceiver datasheet contains instructions for the proper calibration sequence to make it work when the PLL is configured for phase aligned mode. Software has been updated accordingly, so enable phase aligned mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-06 11:33:48 +00:00
set pfdclk_frequency [get_instance_parameter_value link_pll gui_pfd_frequency]
set_instance_parameter_value link_pll {gui_desired_outclk1_frequency} $pfdclk_frequency
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set outclk_name "outclk0"
add_instance link_pll_reset_control altera_xcvr_reset_control $version
set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0}
set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency
set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1}
set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000}
set_instance_parameter_value link_pll_reset_control {TX_ENABLE} {0}
set_instance_parameter_value link_pll_reset_control {RX_ENABLE} {0}
add_connection sys_clock.clk link_pll_reset_control.clock
add_connection link_reset.out_reset link_pll_reset_control.reset
add_connection sys_clock.clk_reset link_pll_reset_control.reset
add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown
} elseif {$device_family == "Stratix 10"} {
send_message info "Instantiate a fpll_s10_htile for link_pll."
add_instance link_pll altera_xcvr_fpll_s10_htile 19.1.1
## Primary Use is Core mode
set_instance_parameter_value link_pll {set_primary_use} 0
## Basic Mode
set_instance_parameter_value link_pll {set_prot_mode} 0
set_instance_parameter_value link_pll {message_level} {error}
set_instance_parameter_value link_pll {set_refclk_cnt} {1}
set_instance_parameter_value link_pll {set_auto_reference_clock_frequency} $refclk_frequency
set_instance_parameter_value link_pll {set_output_clock_frequency} $linkclk_frequency
set_instance_parameter_value link_pll {set_bw_sel} {medium}
set_instance_parameter_value link_pll {rcfg_enable} {1}
set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
set outclk_name "outclk_div1"
} else {
## Unsupported device
send_message error "Only Arria 10 and Stratix 10 are supported."
}
add_connection link_pll.$outclk_name link_clock.in_clk
add_interface link_clk clock source
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
add_connection sys_clock.clk link_reset.clk
altera: adi_jesd204: Export link domain reset Export the reset signal for the link clock domain. This can be used by external logic that is in the link clock domain to reset itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 10:50:45 +00:00
add_interface link_reset reset source
set_interface_property link_reset EXPORT_OF link_reset.out_reset_1
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set_instance_parameter_value link_pll {set_capability_reg_enable} {1}
set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1}
set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1}
add_connection ref_clock.out_clk link_pll.pll_refclk0
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
add_connection sys_clock.clk_reset link_pll.reconfig_reset0
add_connection sys_clock.clk link_pll.reconfig_clk0
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance axi_xcvr axi_adxcvr 1.0
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value axi_xcvr {ID} $id
set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n
set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes
add_connection sys_clock.clk axi_xcvr.s_axi_clock
add_connection sys_clock.clk_reset axi_xcvr.s_axi_reset
add_connection axi_xcvr.if_up_rst link_reset.in_reset
add_connection link_pll.pll_locked axi_xcvr.core_pll_locked
add_interface link_management axi4lite slave
set_interface_property link_management EXPORT_OF axi_xcvr.s_axi
add_interface link_pll_reconfig avalon slave
set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set_interface_property link_pll_reconfig associatedClock sys_clk
set_interface_property link_pll_reconfig associatedReset sys_resetn
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance phy jesd204_phy 1.0
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value phy ID $id
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set_instance_parameter_value phy DEVICE $device_family
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value phy SOFT_PCS $soft_pcs
set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n
set_instance_parameter_value phy LANE_RATE $lane_rate
set_instance_parameter_value phy REFCLK_FREQUENCY $refclk_frequency
set_instance_parameter_value phy NUM_OF_LANES $num_of_lanes
intel/adi_jesd204: Expose REGISTER_INPUTS parameter Define INPUT_PIPELINE parameter, which can be used to activate the REGISTER_INPUTS parameter of the PHY. This parameter will add an additional register stage into the incoming parallel data stream. It can be used to relax the timing margin between the PHY and Link modules.
2020-02-05 14:26:21 +00:00
set_instance_parameter_value phy REGISTER_INPUTS $input_pipeline
altera: jesd204: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the adi_jesd204 and jesd204_phy for Altera modules. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded depending on whether soft or hard PCS is used to either the soft PCS module or the transceiver block itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-19 14:51:56 +00:00
set_instance_parameter_value phy LANE_INVERT $lane_invert
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
set_instance_parameter_value phy BONDING_CLOCKS_EN $bonding_clocks_en
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
add_connection link_reset.out_reset phy.link_reset
add_connection sys_clock.clk phy.reconfig_clk
add_connection sys_clock.clk_reset phy.reconfig_reset
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
## connect the required device clock
if {$ext_device_clk_en} {
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance ext_device_clock altera_clock_bridge $version
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $deviceclk_frequency*1000000]
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2
add_interface device_clk clock sink
set_interface_property device_clk EXPORT_OF ext_device_clock.in_clk
}
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
add_connection $link_clock phy.link_clk
set_interface_property link_clk EXPORT_OF $device_clock_export
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
if {$tx_or_rx_n} {
set tx_rx "tx"
set data_direction sink
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set jesd204_intfs {config device_config control ilas_config device_event status}
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
set phy_reset_intfs {analogreset digitalreset cal_busy}
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en
if {$num_of_lanes > 6} {
intel/adi_jesd204: add bonded clock network support (#408) * jesd204b: add bonding clocks feature (fix for some routing issues) * intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6 * intel/adi_jesd204: clock network option renamed according to intel documentation * intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 15:45:32 +00:00
if {$bonding_clocks_en} {
add_connection lane_pll.tx_bonding_clocks phy.bonding_clocks
} else {
add_connection lane_pll.tx_serial_clk phy.serial_clk_x1
add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN
}
} else {
add_connection lane_pll.tx_serial_clk phy.serial_clk_x1
altera: adi_jesd204: Add support for more than 6 transmit lanes On Arria10 there are 6 transceivers in a single bank. If more than 6 transceivers are used these will end up in multiple banks. The ATX PLL can directly connect to the transceivers in the same bank through the 1x clock network. To connect to transceivers in another bank it has to go through a master clock generation block (MCGB) and the xN clock network. Add support for instantiating the MCGB if more than 6 lanes are used. In this case the first 6 transceivers will still have a direct connection to the PLL while all other transceivers will be clocked by the MCGB. Note that this requires that the first 6 transceivers are all in the same bank. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-03-19 14:51:12 +00:00
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
} else {
set tx_rx "rx"
set data_direction source
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set jesd204_intfs {config device_config ilas_config device_event status}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set phy_reset_intfs {analogreset digitalreset cal_busy is_lockedtodata}
add_connection ref_clock.out_clk phy.ref_clk
}
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} 1.0
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock
add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset
adi_jesd204: add_instance command must have a version attribute
2019-05-13 12:33:55 +00:00
add_instance jesd204_${tx_rx} jesd204_${tx_rx} 1.0
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
set_instance_parameter_value jesd204_${tx_rx} {ASYNC_CLK} $dual_clk_mode
set_instance_parameter_value jesd204_${tx_rx} {TPL_DATA_PATH_WIDTH} $tpl_data_path_width
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
add_connection $link_clock axi_jesd204_${tx_rx}.core_clock
add_connection $device_clock axi_jesd204_${tx_rx}.device_clock
add_connection $link_clock jesd204_${tx_rx}.clock
add_connection $device_clock jesd204_${tx_rx}.device_clock
intel/adi_jesd204: Add support for external core clock In Subclass 1 mode, we need to use a separate clock (device clock) to drive the link and transport layer of the interface. Implement the required infrastructure for this scenario. The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-08-23 12:56:43 +00:00
add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
add_connection axi_jesd204_${tx_rx}.core_reset jesd204_${tx_rx}.reset
jesd204: Intel: NP12 support Dual clock mode is introduced in link layer to support different datapath widths on the transport layer than on physical layer. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - Device clock : Link clock * input data path width / output datapath width Supports four clock configurations, single or dual clock mode with or without external device clock. The configuration interface reflects the dual clock domain.
2020-12-11 13:30:00 +00:00
add_connection axi_jesd204_${tx_rx}.device_reset jesd204_${tx_rx}.device_reset
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
foreach intf $jesd204_intfs {
add_connection axi_jesd204_${tx_rx}.${intf} jesd204_${tx_rx}.${intf}
}
foreach intf $phy_reset_intfs {
add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf}
}
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
## connect phy_reset_control interfaces specific to Stratix 10
if {$device_family == "Stratix 10"} {
foreach intf $phy_reset_intfs_s10 {
add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf}
}
}
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
set lane_map [regexp -all -inline {\S+} $lane_map]
for {set i 0} {$i < $num_of_lanes} {incr i} {
if {$lane_map != {}} {
set j [lindex $lane_map $i]
} else {
set j $i
}
add_connection jesd204_${tx_rx}.${tx_rx}_phy${j} phy.phy_${i}
}
for {set i 0} {$i < $num_of_lanes} {incr i} {
add_interface phy_reconfig_${i} avalon slave
set_interface_property phy_reconfig_${i} EXPORT_OF phy.reconfig_avmm_${i}
}
add_interface interrupt interrupt end
set_interface_property interrupt EXPORT_OF axi_jesd204_${tx_rx}.interrupt
add_interface link_reconfig axi4lite slave
set_interface_property link_reconfig EXPORT_OF axi_jesd204_${tx_rx}.s_axi
add_interface link_data avalon_streaming $data_direction
set_interface_property link_data EXPORT_OF jesd204_${tx_rx}.${tx_rx}_data
if {!$tx_or_rx_n} {
add_interface link_sof conduit end
set_interface_property link_sof EXPORT_OF jesd204_rx.rx_sof
}
add_interface sysref conduit end
set_interface_property sysref EXPORT_OF jesd204_${tx_rx}.sysref
add_interface sync conduit end
set_interface_property sync EXPORT_OF jesd204_${tx_rx}.sync
add_interface serial_data conduit end
set_interface_property serial_data EXPORT_OF phy.serial_data
jesd204_framework: Add Stratix10 support This patch contains an initial effort to support the Stratix 10 architecture in our JESD204 framework. Several instances were updated, doing simple context switching using the DEVICE_FAMILY system parameter: - xcvr_reset_control - lane PLL (ATX PLL) - link PLL (fPLL) - native XCVR instance Apart from the slightly different parameters of the instances above, there were small differences at the reconfiguration Avalon_MM interface. The link_pll_reset_control is required just for Arria10, so in case of Stratix10 it isn't instantiated. In Stratix 10 architecture there are several additional ports of the xcvr_reset_control module that must be connected to the native XCVR instance or tied to GND. The following xcvr_reset_control ports were defined and connected to the XCVR: - rx|tx_analogreset_stat - rx|tx_digitalreset_stat - pll_select
2019-04-16 07:18:28 +00:00
library: Add ADI JESD204 wrapper for Altera/Intel platforms Add a wrapper module for Altera/Intel platforms that instantiates and connects all the components required to for a JESD204 link. The following components are created: * Transceiver for each lane * Transceiver lane PLL (TX only) * Transceiver reset controller * Link PLL * JESD204 link layer processing * JESD204 link layer processing control interface * axi_adxcvr link management peripheral Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 19:25:55 +00:00
}