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pluto_hdl_adi/library/xilinx/util_adxcvr/util_adxcvr_xch.v

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util_adxcvr- added
2016-06-14 16:18:56 +00:00
// ***************************************************************************
// ***************************************************************************
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
util_adxcvr: Delete trailing whitespaces
2016-10-05 10:51:39 +00:00
//
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
license: Fix a spelling mistake
2018-03-14 14:45:47 +00:00
// freedoms and responsibilities that he or she has by using this source/core.
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
util_adxcvr: Delete trailing whitespaces
2016-10-05 10:51:39 +00:00
//
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
util_adxcvr: Delete trailing whitespaces
2016-10-05 10:51:39 +00:00
//
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
// 1. The GNU General Public License version 2 as published by the
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
all: Update license for all hdl source files All the hdl (verilog and vhdl) source files were updated. If a file did not have any license, it was added into it. Files, which were generated by a tool (like Matlab) or were took over from other source (like opencores.org), were unchanged. New license looks as follows: Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. Each core or library found in this collection may have its own licensing terms. The user should keep this in in mind while exploring these cores. Redistribution and use in source and binary forms, with or without modification of this file, are permitted under the terms of either (at the option of the user): 1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory, or at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html OR 2. An ADI specific BSD license as noted in the top level directory, or on-line at: https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 08:44:52 +00:00
//
// OR
//
license: Add some clarification to the header license
2017-05-31 15:15:24 +00:00
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
license: Update license terms in hdl source files Fix a few gramatical error, fix the path of the top level license files.
2017-05-29 06:55:41 +00:00
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
util_adxcvr- added
2016-06-14 16:18:56 +00:00
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
util_adxcvr- xcvr_type parameter
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module util_adxcvr_xch #(
// parameters
parameter integer XCVR_TYPE = 0,
util_adxcvr- parameter defaults
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util_adxcvr- xcvr_type parameter
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parameter integer CPLL_FBDIV = 2,
util_adxcvr- parameter defaults
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parameter integer CPLL_FBDIV_4_5 = 5,
util_adxcvr: Expose QPLL and CPLL *_CFG attributes
2018-10-02 14:19:35 +00:00
parameter [15:0] CPLL_CFG0 = 16'b0000000111111010,
parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
util_adxcvr- parameter defaults
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util_adxcvr- xcvr_type parameter
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parameter integer TX_OUT_DIV = 1,
util_adxcvr- parameter defaults
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parameter integer TX_CLK25_DIV = 20,
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
parameter integer TX_POLARITY = 0,
util_adxcvr- parameter defaults
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parameter integer RX_OUT_DIV = 1,
parameter integer RX_CLK25_DIV = 20,
fmcomms11- xcvr updates
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parameter [15:0] RX_DFE_LPM_CFG = 16'h0104,
util_adxcvr- parameter defaults
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parameter [31:0] RX_PMA_CFG = 32'h001e7080,
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020,
parameter integer RX_POLARITY = 0) (
util_adxcvr- added
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util_adxcvr: shared xcvr cores
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// pll interface
util_adxcvr- added
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util_adxcvr: shared xcvr cores
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input qpll2ch_clk,
input qpll2ch_ref_clk,
input qpll2ch_locked,
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
input qpll1_clk,
input qpll1_ref_clk,
input qpll1_locked,
util_adxcvr: shared xcvr cores
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input cpll_ref_clk,
util_adxcvr: expose cpll/qpll as it is
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input up_cpll_rst,
util_adxcvr- added
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// receive
input rx_p,
input rx_n,
output rx_out_clk,
util_adxcvr: shared xcvr cores
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input rx_clk,
output [ 3:0] rx_charisk,
output [ 3:0] rx_disperr,
output [ 3:0] rx_notintable,
output [31:0] rx_data,
input rx_calign,
util_adxcvr- added
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// transmit
output tx_p,
output tx_n,
output tx_out_clk,
util_adxcvr: shared xcvr cores
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input tx_clk,
input [ 3:0] tx_charisk,
input [31:0] tx_data,
util_adxcvr- added
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util_adxcvr: shared xcvr cores
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// up interface
util_adxcvr- added
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input up_rstn,
input up_clk,
util_adxcvr: shared xcvr cores
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input up_es_enb,
input [11:0] up_es_addr,
input up_es_wr,
input [15:0] up_es_wdata,
output [15:0] up_es_rdata,
output up_es_ready,
axi/util_adxcvr: Add register to control eyescan reset
2018-11-08 13:54:15 +00:00
input up_es_reset,
util_adxcvr: shared xcvr cores
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output up_rx_pll_locked,
input up_rx_rst,
input up_rx_user_ready,
output up_rx_rst_done,
input up_rx_lpm_dfe_n,
input [ 2:0] up_rx_rate,
input [ 1:0] up_rx_sys_clk_sel,
input [ 2:0] up_rx_out_clk_sel,
input up_rx_enb,
input [11:0] up_rx_addr,
input up_rx_wr,
input [15:0] up_rx_wdata,
output [15:0] up_rx_rdata,
output up_rx_ready,
output up_tx_pll_locked,
input up_tx_rst,
input up_tx_user_ready,
output up_tx_rst_done,
input up_tx_lpm_dfe_n,
input [ 2:0] up_tx_rate,
input [ 1:0] up_tx_sys_clk_sel,
input [ 2:0] up_tx_out_clk_sel,
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
input [ 3:0] up_tx_diffctrl,
input [ 4:0] up_tx_postcursor,
input [ 4:0] up_tx_precursor,
util_adxcvr: shared xcvr cores
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input up_tx_enb,
input [11:0] up_tx_addr,
input up_tx_wr,
input [15:0] up_tx_wdata,
output [15:0] up_tx_rdata,
output up_tx_ready);
util_adxcvr- added
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// internal registers
util_adxcvr: shared xcvr cores
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reg [15:0] up_es_rdata_int = 'd0;
reg up_es_ready_int = 'd0;
reg [15:0] up_rx_rdata_int = 'd0;
reg up_rx_ready_int = 'd0;
reg [15:0] up_tx_rdata_int = 'd0;
reg up_tx_ready_int = 'd0;
reg [ 2:0] up_sel_int = 'd0;
reg up_enb_int = 'd0;
reg [11:0] up_addr_int = 'd0;
reg up_wr_int = 'd0;
reg [15:0] up_wdata_int = 'd0;
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
reg up_rx_rst_done_m1 = 'd0;
reg up_rx_rst_done_m2 = 'd0;
reg up_tx_rst_done_m1 = 'd0;
reg up_tx_rst_done_m2 = 'd0;
reg [ 2:0] rx_rate_m1 = 'd0;
reg [ 2:0] rx_rate_m2 = 'd0;
reg [ 2:0] tx_rate_m1 = 'd0;
reg [ 2:0] tx_rate_m2 = 'd0;
util_adxcvr- added
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// internal signals
util_adxcvr: shared xcvr cores
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wire [15:0] up_rdata_s;
wire up_ready_s;
util_adxcvr- added
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wire [ 1:0] rx_sys_clk_sel_s;
util_adxcvr- add clock buffers, rst-done, rate on usrclk
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wire rx_out_clk_s;
wire rx_rst_done_s;
util_adxcvr- added
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wire [ 1:0] tx_sys_clk_sel_s;
util_adxcvr- add clock buffers, rst-done, rate on usrclk
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wire tx_out_clk_s;
wire tx_rst_done_s;
util_adxcvr- added
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wire [ 1:0] rx_pll_clk_sel_s;
wire [ 1:0] tx_pll_clk_sel_s;
util_adxcvr- synthesis warnings fix
2016-09-30 19:25:03 +00:00
wire [11:0] rx_charisk_open_s;
wire [11:0] rx_disperr_open_s;
util_adxcvr: shared xcvr cores
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wire [ 3:0] rx_notintable_open_s;
util_adxcvr- synthesis warnings fix
2016-09-30 19:25:03 +00:00
wire [95:0] rx_data_open_s;
util_adxcvr- added
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wire cpll_locked_s;
util_adxcvr: shared xcvr cores
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// pll
util_adxcvr- added
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util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : (up_rx_sys_clk_sel == 2'd2) ? qpll1_locked : cpll_locked_s;
assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : (up_tx_sys_clk_sel == 2'd2) ? qpll1_locked : cpll_locked_s;
util_adxcvr- added
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// drp access
util_adxcvr: shared xcvr cores
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assign up_es_rdata = up_es_rdata_int;
assign up_es_ready = up_es_ready_int;
assign up_rx_rdata = up_rx_rdata_int;
assign up_rx_ready = up_rx_ready_int;
assign up_tx_rdata = up_tx_rdata_int;
assign up_tx_ready = up_tx_ready_int;
always @(negedge up_rstn or posedge up_clk) begin
util_adxcvr- added
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if (up_rstn == 1'b0) begin
util_adxcvr: shared xcvr cores
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up_es_rdata_int <= 15'd0;
up_es_ready_int <= 1'd0;
up_rx_rdata_int <= 15'd0;
up_rx_ready_int <= 1'd0;
up_tx_rdata_int <= 15'd0;
up_tx_ready_int <= 1'd0;
up_sel_int <= 3'd0;
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end else begin
util_adxcvr: shared xcvr cores
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if (up_sel_int == 3'b100) begin
up_es_rdata_int <= up_rdata_s;
up_es_ready_int <= up_ready_s;
end else begin
up_es_rdata_int <= 15'd0;
up_es_ready_int <= 1'd0;
end
if (up_sel_int == 3'b101) begin
up_rx_rdata_int <= up_rdata_s;
up_rx_ready_int <= up_ready_s;
end else begin
up_rx_rdata_int <= 15'd0;
up_rx_ready_int <= 1'd0;
end
if (up_sel_int == 3'b110) begin
up_tx_rdata_int <= up_rdata_s;
up_tx_ready_int <= up_ready_s;
end else begin
up_tx_rdata_int <= 15'd0;
up_tx_ready_int <= 1'd0;
end
if (up_sel_int[2] == 1'b1) begin
if (up_ready_s == 1'b1) begin
up_sel_int <= 3'b000;
end
up_enb_int <= 1'b0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
end else if (up_es_enb == 1'b1) begin
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
up_sel_int <= 3'b100;
up_enb_int <= 1'b1;
up_addr_int <= up_es_addr;
up_wr_int <= up_es_wr;
up_wdata_int <= up_es_wdata;
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
end else if (up_rx_enb == 1'b1) begin
util_adxcvr: shared xcvr cores
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up_sel_int <= 3'b101;
up_enb_int <= 1'b1;
up_addr_int <= up_rx_addr;
up_wr_int <= up_rx_wr;
up_wdata_int <= up_rx_wdata;
axi_adxcvr/util_adxcvr: Fix non-broadcast DRP access When using non-broadcast access to the GT DRP registers lane filtering is done on both sides. The ready and data signals are filtered in the in the axi_adxcvr module and the enable signal is filtered in the util_adxcvr module. This works fine as long as both sides use the same transceiver IDs. E.g. channel 0 of the axi_adxcvr module is connected to channel 0 of the util_adxcvr module. But this is not always the case. E.g. on the ADRV9371 platform there are two RX axi_adxcvr modules (RX and RX_OS) connected to the same util_adxcvr. The first axi_adxcvr uses lane 0 and 1 of the util_adxcvr, the second uses lane 2 and 3. Non-broadcast access for the first RX axi_adxcvr module works fine, but always generates a timeout for the second axi_adxcvr module. This is because lane 0/1 of the axi_adxcvr module is connected to lane 2/3 of the util_adxcvr and when ID based filtering is done both can't match at the same time. To avoid this perform the filtering for all the signals in the axi_adxcvr module. This makes sure that the same base ID is used. This also removes the sel signal from the transceiver interfaces since it is no longer used on the util_adxcvr side. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-28 14:22:10 +00:00
end else if (up_tx_enb == 1'b1) begin
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
up_sel_int <= 3'b110;
up_enb_int <= 1'b1;
up_addr_int <= up_tx_addr;
up_wr_int <= up_tx_wr;
up_wdata_int <= up_tx_wdata;
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end else begin
util_adxcvr: shared xcvr cores
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up_sel_int <= 3'b000;
up_enb_int <= 1'b0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 15'd0;
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end
end
end
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
assign up_rx_rst_done = up_rx_rst_done_m2;
assign up_tx_rst_done = up_tx_rst_done_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rx_rst_done_m1 <= 'd0;
up_rx_rst_done_m2 <= 'd0;
up_tx_rst_done_m1 <= 'd0;
up_tx_rst_done_m2 <= 'd0;
end else begin
up_rx_rst_done_m1 <= rx_rst_done_s;
up_rx_rst_done_m2 <= up_rx_rst_done_m1;
up_tx_rst_done_m1 <= tx_rst_done_s;
up_tx_rst_done_m2 <= up_tx_rst_done_m1;
end
end
always @(posedge rx_clk) begin
rx_rate_m1 <= up_rx_rate;
rx_rate_m2 <= rx_rate_m1;
end
always @(posedge tx_clk) begin
tx_rate_m1 <= up_tx_rate;
tx_rate_m2 <= tx_rate_m1;
end
util_adxcvr- added
2016-06-14 16:18:56 +00:00
// instantiations
adxcvr- add u-gth bufg
2016-08-11 13:59:15 +00:00
generate
util_adxcvr- xcvr_type parameter
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if (XCVR_TYPE == 0) begin
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
BUFG i_rx_bufg (.I (rx_out_clk_s), .O (rx_out_clk));
BUFG i_tx_bufg (.I (tx_out_clk_s), .O (tx_out_clk));
adxcvr- add u-gth bufg
2016-08-11 13:59:15 +00:00
end
endgenerate
util_adxcvr- added
2016-06-14 16:18:56 +00:00
generate
util_adxcvr- xcvr_type parameter
2016-10-03 18:08:19 +00:00
if (XCVR_TYPE == 0) begin
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
assign tx_sys_clk_sel_s = up_tx_sys_clk_sel;
util_adxcvr- added
2016-06-14 16:18:56 +00:00
assign rx_pll_clk_sel_s = 2'd0;
assign tx_pll_clk_sel_s = 2'd0;
end
endgenerate
generate
util_adxcvr- xcvr_type parameter
2016-10-03 18:08:19 +00:00
if (XCVR_TYPE == 0) begin
util_adxcvr- added
2016-06-14 16:18:56 +00:00
GTXE2_CHANNEL #(
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.ALIGN_COMMA_WORD (4),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.CHAN_BOND_MAX_SKEW (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.CHAN_BOND_SEQ_LEN (1),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0000000000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_SEQ_LEN (1),
.CPLL_CFG (24'hBC07DC),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG (24'h00001E),
.CPLL_LOCK_CFG (16'h01E8),
.CPLL_REFCLK_DIV (1),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DMONITOR_CFG (24'h000A00),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
.ES_HORZ_OFFSET (12'h000),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (80'h00000000000000000000),
util_adxcvr- defaults for es
2017-08-08 15:03:38 +00:00
.ES_QUAL_MASK (80'hffffffffffffffffffff),
.ES_SDATA_MASK (80'hffffffffff0000000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ES_VERT_OFFSET (9'b000000000),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
.IS_CPLLLOCKDETCLK_INVERTED (1'b0),
.IS_DRPCLK_INVERTED (1'b0),
.IS_GTGREFCLK_INVERTED (1'b0),
.IS_RXUSRCLK2_INVERTED (1'b0),
.IS_RXUSRCLK_INVERTED (1'b0),
.IS_TXPHDLYTSTCLK_INVERTED (1'b0),
.IS_TXUSRCLK2_INVERTED (1'b0),
.IS_TXUSRCLK_INVERTED (1'b0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.OUTREFCLK_SEL_INV (2'b11),
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD_ATTR (48'h000000000000),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
.PMA_RSV (RX_PMA_CFG),
util_adxcvr- defaults for es
2017-08-08 15:03:38 +00:00
.PMA_RSV2 (16'h2070),
util_adxcvr- parameter defaults
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.PMA_RSV3 (2'b00),
.PMA_RSV4 (32'h00000000),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_ADDR_MODE ("FAST"),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCDR_CFG (RX_CDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b010101),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXDFELPMRESET_TIME (7'b0001111),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (9'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXGEARBOX_EN ("FALSE"),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXISCANRESET_TIME (5'b00001),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXLPM_HF_CFG (14'b00000011110000),
.RXLPM_LF_CFG (14'b00000011110000),
.RXOOB_CFG (7'b0000110),
.RXOUT_DIV (RX_OUT_DIV),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPCSRESET_TIME (5'b00001),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXPHDLY_CFG (24'h084020),
.RXPH_CFG (24'h000000),
.RXPH_MONITOR_SEL (5'b00000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_BIAS_CFG (12'b000000000100),
.RX_BUFFER_CFG (6'b000000),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_PD (1'b1),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (3'b010),
.RX_DATA_WIDTH (40),
.RX_DDI_SEL (6'b000000),
.RX_DEBUG_CFG (12'b000000000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DFE_GAIN_CFG (23'h020FEA),
.RX_DFE_H2_CFG (12'b000000000000),
.RX_DFE_H3_CFG (12'b000001000000),
.RX_DFE_H4_CFG (11'b00011110000),
.RX_DFE_H5_CFG (11'b00011100000),
.RX_DFE_KL_CFG (13'b0000011111110),
.RX_DFE_KL_CFG2 (32'h301148AC),
fmcomms11- xcvr updates
2016-10-24 13:51:29 +00:00
.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DFE_UT_CFG (17'b10001111000000000),
.RX_DFE_VP_CFG (17'b00011111100000011),
.RX_DFE_XYD_CFG (13'b0000000000000),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_INT_DATAWIDTH (1),
.RX_OS_CFG (13'b0000010000000),
.RX_SIG_VALID_DLY (10),
.RX_XCLK_SEL ("RXREC"),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.SATA_BURST_SEQ_LEN (4'b0101),
.SATA_BURST_VAL (3'b111),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b111),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_CPLLREFCLK_SEL (3'b001),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_VERSION ("4.0"),
.TERM_RCAL_CFG (5'b10000),
.TERM_RCAL_OVRD (1'b0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TRANS_TIME_RATE (8'h0E),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TST_RSV (32'h00000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (9'h030),
.TXDLY_TAP_CFG (16'h0000),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXGEARBOX_EN ("FALSE"),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00001),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPHDLY_CFG (24'h084020),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXPH_CFG (16'h0780),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPH_MONITOR_SEL (5'b00000),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXPMARESET_TIME (5'b00001),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_PD (1'b1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_DATA_WIDTH (40),
.TX_DEEMPH0 (5'b00000),
.TX_DEEMPH1 (5'b00000),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TX_DRIVE_MODE ("DIRECT"),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TX_INT_DATAWIDTH (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TX_PREDRIVER_MODE (1'b0),
.TX_QPI_STATUS_EN (1'b0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_RXDETECT_CFG (14'h1832),
.TX_RXDETECT_REF (3'b100),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TX_XCLK_SEL ("TXOUT"),
.UCODEER_CLR (1'b0))
util_adxcvr- added
2016-06-14 16:18:56 +00:00
i_gtxe2_channel (
Fix warnings
2016-11-14 13:17:15 +00:00
.RXOUTCLKPCS (),
.RXPHSLIPMONITOR (),
.PHYSTATUS (),
.RXCDRLOCK (),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCOMINITDET (),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXDATAVALID (),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXHEADERVALID (),
.RXPHALIGNDONE (),
.RXQPISENN (),
.RXQPISENP (),
.RXRATEDONE (),
.RXSTARTOFSEQ (),
.RXVALID (),
.TXCOMFINISH (),
.TXDLYSRESETDONE (),
.TXGEARBOXREADY (),
.TXPHALIGNDONE (),
.TXPHINITDONE (),
.TXQPISENN (),
.TXQPISENP (),
.TXRATEDONE (),
.PCSRSVDOUT (),
.RXCLKCORCNT (),
.RXHEADER (),
.RXCHBONDO (),
.RXPHMONITOR (),
.TSTOUT (),
.GTREFCLKMONITOR (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.CFGRESET (1'h0),
.CLKRSVD (4'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
.CPLLLOCKDETCLK (up_clk),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.CPLLLOCKEN (1'h1),
.CPLLPD (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CPLLREFCLKLOST (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.CPLLREFCLKSEL (3'h1),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.CPLLRESET (up_cpll_rst),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.DMONITOROUT (),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPADDR (up_addr_int[8:0]),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.DRPCLK (up_clk),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPWE (up_wr_int),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.EYESCANDATAERROR (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.EYESCANMODE (1'h0),
.EYESCANRESET (1'h0),
.EYESCANTRIGGER (1'h0),
.GTGREFCLK (1'h0),
.GTNORTHREFCLK0 (1'h0),
.GTNORTHREFCLK1 (1'h0),
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'h0),
.GTRESETSEL (1'h0),
.GTRSVD (16'h0),
.GTRXRESET (up_rx_rst),
.GTSOUTHREFCLK0 (1'h0),
.GTSOUTHREFCLK1 (1'h0),
.GTTXRESET (up_tx_rst),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.GTXRXN (rx_n),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.GTXRXP (rx_p),
.GTXTXN (tx_n),
.GTXTXP (tx_p),
.LOOPBACK (3'h0),
.PCSRSVDIN (16'h0),
.PCSRSVDIN2 (5'h0),
.PMARSVDIN (5'h0),
.PMARSVDIN2 (5'h0),
.QPLLCLK (qpll2ch_clk),
.QPLLREFCLK (qpll2ch_ref_clk),
.RESETOVRD (1'h0),
.RX8B10BEN (1'h1),
.RXBUFRESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXCDRFREQRESET (1'h0),
.RXCDRHOLD (1'h0),
.RXCDROVRDEN (1'h0),
.RXCDRRESET (1'h0),
.RXCDRRESETRSV (1'h0),
.RXCHARISCOMMA (),
.RXCHARISK ({rx_charisk_open_s[3:0], rx_charisk}),
.RXCHBONDEN (1'h0),
.RXCHBONDI (5'h0),
.RXCHBONDLEVEL (3'h0),
.RXCHBONDMASTER (1'h1),
.RXCHBONDSLAVE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCOMMADET (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXCOMMADETEN (1'h1),
.RXDATA ({rx_data_open_s[31:0], rx_data}),
.RXDDIEN (1'h0),
.RXDFEAGCHOLD (1'h0),
.RXDFEAGCOVRDEN (1'h0),
.RXDFECM1EN (1'h0),
.RXDFELFHOLD (1'h0),
.RXDFELFOVRDEN (1'h0),
.RXDFELPMRESET (1'h0),
.RXDFETAP2HOLD (1'h0),
.RXDFETAP2OVRDEN (1'h0),
.RXDFETAP3HOLD (1'h0),
.RXDFETAP3OVRDEN (1'h0),
.RXDFETAP4HOLD (1'h0),
.RXDFETAP4OVRDEN (1'h0),
.RXDFETAP5HOLD (1'h0),
.RXDFETAP5OVRDEN (1'h0),
.RXDFEUTHOLD (1'h0),
.RXDFEUTOVRDEN (1'h0),
.RXDFEVPHOLD (1'h0),
.RXDFEVPOVRDEN (1'h0),
.RXDFEVSEN (1'h0),
.RXDFEXYDEN (1'h1),
.RXDFEXYDHOLD (1'h0),
.RXDFEXYDOVRDEN (1'h0),
.RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}),
.RXDLYBYPASS (1'h1),
.RXDLYEN (1'h0),
.RXDLYOVRDEN (1'h0),
.RXDLYSRESET (1'h0),
.RXELECIDLEMODE (2'h3),
.RXGEARBOXSLIP (1'h0),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMHFHOLD (1'h0),
.RXLPMHFOVRDEN (1'h0),
.RXLPMLFHOLD (1'h0),
.RXLPMLFKLOVRDEN (1'h0),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.RXMCOMMAALIGNEN (rx_calign),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXMONITOROUT (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXMONITORSEL (2'h0),
.RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}),
.RXOOBRESET (1'h0),
.RXOSHOLD (1'h0),
.RXOSOVRDEN (1'h0),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.RXOUTCLK (rx_out_clk_s),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXOUTCLKFABRIC (),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.RXOUTCLKSEL (up_rx_out_clk_sel),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'h0),
.RXPD (2'h0),
.RXPHALIGN (1'h0),
.RXPHALIGNEN (1'h0),
.RXPHDLYPD (1'h0),
.RXPHDLYRESET (1'h0),
.RXPHOVRDEN (1'h0),
.RXPMARESET (1'h0),
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
.RXPOLARITY (RX_POLARITY),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXPRBSCNTRESET (1'h0),
.RXPRBSERR (),
.RXPRBSSEL (3'h0),
.RXQPIEN (1'h0),
.RXRATE (rx_rate_m2),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.RXRESETDONE (rx_rst_done_s),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.RXSLIDE (1'h0),
.RXSTATUS (),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.SETERRSTATUS (1'h0),
.TSTIN (20'hfffff),
.TX8B10BBYPASS (8'h0),
.TX8B10BEN (1'h1),
.TXBUFDIFFCTRL (3'h4),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXBUFSTATUS (),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXCHARDISPMODE (8'h0),
.TXCHARDISPVAL (8'h0),
.TXCHARISK ({4'd0, tx_charisk}),
.TXCOMINIT (1'h0),
.TXCOMSAS (1'h0),
.TXCOMWAKE (1'h0),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.TXDATA ({32'd0, tx_data}),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXDIFFCTRL (up_tx_diffctrl),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
.TXDLYHOLD (1'h0),
.TXDLYOVRDEN (1'h0),
.TXDLYSRESET (1'h0),
.TXDLYUPDOWN (1'h0),
.TXELECIDLE (1'h0),
.TXHEADER (3'h0),
.TXINHIBIT (1'h0),
.TXMAINCURSOR (7'h0),
.TXMARGIN (3'h0),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.TXOUTCLK (tx_out_clk_s),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.TXOUTCLKSEL (up_tx_out_clk_sel),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXPCSRESET (1'h0),
.TXPD (2'h0),
.TXPDELECIDLEMODE (1'h0),
.TXPHALIGN (1'h0),
.TXPHALIGNEN (1'h0),
.TXPHDLYPD (1'h0),
.TXPHDLYRESET (1'h0),
.TXPHDLYTSTCLK (1'h0),
.TXPHINIT (1'h0),
.TXPHOVRDEN (1'h0),
.TXPISOPD (1'h0),
.TXPMARESET (1'h0),
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
.TXPOLARITY (TX_POLARITY),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXPOSTCURSOR (up_tx_postcursor),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPRBSSEL (3'd0),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXPRECURSOR (up_tx_precursor),
util_adxcvr- parameter defaults
2016-10-17 20:10:48 +00:00
.TXPRECURSORINV (1'h0),
.TXQPIBIASEN (1'h0),
.TXQPISTRONGPDOWN (1'h0),
.TXQPIWEAKPUP (1'h0),
.TXRATE (tx_rate_m2),
.TXRESETDONE (tx_rst_done_s),
.TXSEQUENCE (7'h0),
.TXSTARTSEQ (1'h0),
.TXSWING (1'h0),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk));
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end
endgenerate
util_adxcvr- rx/tx clocks
2016-10-05 17:53:02 +00:00
generate
if (XCVR_TYPE == 1) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
util_adxcvr- added
2016-06-14 16:18:56 +00:00
generate
util_adxcvr- xcvr_type parameter
2016-10-03 18:08:19 +00:00
if (XCVR_TYPE == 1) begin
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]};
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]};
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end
endgenerate
generate
util_adxcvr- xcvr_type parameter
2016-10-03 18:08:19 +00:00
if (XCVR_TYPE == 1) begin
util_adxcvr- added
2016-06-14 16:18:56 +00:00
GTHE3_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.ADAPT_CFG0 (16'hf800),
.ADAPT_CFG1 (16'h0000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.ALIGN_COMMA_WORD (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_TXPROGDIVRESET (1'b0),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CDR_SWAP_MODE_EN (1'b0),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CHAN_BOND_MAX_SKEW (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CHAN_BOND_SEQ_LEN (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CLK_COR_REPEAT_WAIT (0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CLK_COR_SEQ_LEN (1),
util_adxcvr: Expose QPLL and CPLL *_CFG attributes
2018-10-02 14:19:35 +00:00
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3[5:0]),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CPLL_FBDIV (CPLL_FBDIV),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
.CPLL_INIT_CFG0 (16'h02b2),
.CPLL_INIT_CFG1 (8'h00),
.CPLL_LOCK_CFG (16'h01e8),
.CPLL_REFCLK_DIV (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DFE_D_X_REL_POS (1'b0),
.DFE_VCM_COMP_EN (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.DMONITOR_CFG0 (10'h000),
.DMONITOR_CFG1 (8'h00),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.ES_HORZ_OFFSET (12'h000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.ES_QUALIFIER0 (16'h0000),
.ES_QUALIFIER1 (16'h0000),
.ES_QUALIFIER2 (16'h0000),
.ES_QUALIFIER3 (16'h0000),
.ES_QUALIFIER4 (16'h0000),
axi_adxcvr: Fix eyescan support for ultrascale plus devices
2018-10-09 09:44:09 +00:00
.ES_QUAL_MASK0 (16'hffff),
.ES_QUAL_MASK1 (16'hffff),
.ES_QUAL_MASK2 (16'hffff),
.ES_QUAL_MASK3 (16'hffff),
.ES_QUAL_MASK4 (16'hffff),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.ES_SDATA_MASK0 (16'h0000),
.ES_SDATA_MASK1 (16'h0000),
util_adxcvr- defaults for es
2017-08-08 15:03:38 +00:00
.ES_SDATA_MASK2 (16'hff00),
.ES_SDATA_MASK3 (16'hffff),
.ES_SDATA_MASK4 (16'hffff),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.EVODD_PHI_CFG (11'b00000000000),
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (5'b00000),
.GM_BIAS_SELECT (1'b0),
.LOCAL_MASTER (1'b1),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.PCIE_BUFG_DIV_CTRL (16'h1000),
.PCIE_RXPCS_CFG_GEN3 (16'h02a4),
.PCIE_RXPMA_CFG (16'h000a),
.PCIE_TXPCS_CFG_GEN3 (16'h24a4),
.PCIE_TXPMA_CFG (16'h000a),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
.PCS_RSVD1 (3'b000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h19),
.PD_TRANS_TIME_TO_P2 (8'h64),
.PLL_SEL_MODE_GEN12 (2'h3),
.PLL_SEL_MODE_GEN3 (2'h3),
.PMA_RSV1 (16'hf000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PROCESS_PAR (3'b010),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RATE_SW_USE_DRP (1'b1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RESET_POWERSAVE_DISABLE (1'b0),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCDR_CFG0 (16'h0000),
.RXCDR_CFG0_GEN3 (16'h0000),
.RXCDR_CFG1 (16'h0000),
.RXCDR_CFG1_GEN3 (16'h0000),
.RXCDR_CFG2 (16'h0766),
.RXCDR_CFG2_GEN3 (16'h07e6),
.RXCDR_CFG3 (16'h0000),
.RXCDR_CFG3_GEN3 (16'h0000),
.RXCDR_CFG4 (16'h0000),
.RXCDR_CFG4_GEN3 (16'h0000),
.RXCDR_CFG5 (16'h0000),
.RXCDR_CFG5_GEN3 (16'h0000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCDR_LOCK_CFG0 (16'h4480),
.RXCDR_LOCK_CFG1 (16'h5fff),
.RXCDR_LOCK_CFG2 (16'h77c3),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCFOK_CFG0 (16'h4000),
.RXCFOK_CFG1 (16'h0065),
.RXCFOK_CFG2 (16'h002e),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXDFELPMRESET_TIME (7'b0001111),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXDFELPM_KL_CFG0 (16'h0000),
.RXDFELPM_KL_CFG1 (16'h0032),
.RXDFELPM_KL_CFG2 (16'h0000),
.RXDFE_CFG0 (16'h0a00),
.RXDFE_CFG1 (16'h0000),
.RXDFE_GC_CFG0 (16'h0000),
.RXDFE_GC_CFG1 (16'h7870),
.RXDFE_GC_CFG2 (16'h0000),
.RXDFE_H2_CFG0 (16'h0000),
.RXDFE_H2_CFG1 (16'h0000),
.RXDFE_H3_CFG0 (16'h4000),
.RXDFE_H3_CFG1 (16'h0000),
.RXDFE_H4_CFG0 (16'h2000),
.RXDFE_H4_CFG1 (16'h0003),
.RXDFE_H5_CFG0 (16'h2000),
.RXDFE_H5_CFG1 (16'h0003),
.RXDFE_H6_CFG0 (16'h2000),
.RXDFE_H6_CFG1 (16'h0000),
.RXDFE_H7_CFG0 (16'h2000),
.RXDFE_H7_CFG1 (16'h0000),
.RXDFE_H8_CFG0 (16'h2000),
.RXDFE_H8_CFG1 (16'h0000),
.RXDFE_H9_CFG0 (16'h2000),
.RXDFE_H9_CFG1 (16'h0000),
.RXDFE_HA_CFG0 (16'h2000),
.RXDFE_HA_CFG1 (16'h0000),
.RXDFE_HB_CFG0 (16'h2000),
.RXDFE_HB_CFG1 (16'h0000),
.RXDFE_HC_CFG0 (16'h0000),
.RXDFE_HC_CFG1 (16'h0000),
.RXDFE_HD_CFG0 (16'h0000),
.RXDFE_HD_CFG1 (16'h0000),
.RXDFE_HE_CFG0 (16'h0000),
.RXDFE_HE_CFG1 (16'h0000),
.RXDFE_HF_CFG0 (16'h0000),
.RXDFE_HF_CFG1 (16'h0000),
.RXDFE_OS_CFG0 (16'h8000),
.RXDFE_OS_CFG1 (16'h0000),
.RXDFE_UT_CFG0 (16'h8000),
.RXDFE_UT_CFG1 (16'h0003),
.RXDFE_VP_CFG0 (16'haa00),
.RXDFE_VP_CFG1 (16'h0033),
.RXDLY_CFG (16'h001f),
.RXDLY_LCFG (16'h0030),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXELECIDLE_CFG ("Sigcfg_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (4),
.RXGEARBOX_EN ("FALSE"),
.RXISCANRESET_TIME (5'b00001),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXLPM_CFG (16'h0000),
.RXLPM_GC_CFG (16'h1000),
.RXLPM_KH_CFG0 (16'h0000),
.RXLPM_KH_CFG1 (16'h0002),
.RXLPM_OS_CFG0 (16'h8000),
.RXLPM_OS_CFG1 (16'h0002),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPHBEACON_CFG (16'h0000),
.RXPHDLY_CFG (16'h2020),
.RXPHSAMP_CFG (16'h2100),
.RXPHSLIP_CFG (16'h6622),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPH_MONITOR_SEL (5'b00000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPI_CFG0 (2'b01),
.RXPI_CFG1 (2'b01),
.RXPI_CFG2 (2'b01),
.RXPI_CFG3 (2'b01),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPI_CFG4 (1'b0),
.RXPI_CFG5 (1'b1),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPI_CFG6 (3'b011),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPI_LPM (1'b0),
.RXPI_VREFSEL (1'b0),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_BIAS_CFG0 (16'h0ab4),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (2'b11),
.RX_CM_TRIM (4'b1010),
.RX_CTLE3_LPF (8'b00000001),
.RX_DATA_WIDTH (40),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DFELPM_CFG0 (4'b0110),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG0 (2'b10),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_DFE_AGC_CFG1 (3'b000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_DFE_KL_LPM_KH_CFG0 (2'b01),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_DFE_KL_LPM_KH_CFG1 (3'b000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_DFE_KL_LPM_KL_CFG0 (2'b01),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_DFE_KL_LPM_KL_CFG1 (3'b000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_HI_LR (1'b1),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b00),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_INT_DATAWIDTH (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_PMA_POWER_SAVE (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_PROGDIV_CFG (0.000000),
.RX_SAMPLE_PERIOD (3'b111),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_SIG_VALID_DLY (11),
.RX_SUM_DFETAPREP_EN (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RX_SUM_IREF_TUNE (4'b1100),
.RX_SUM_RES_CTRL (2'b11),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RX_SUM_VCMTUNE (4'b0000),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b000),
.RX_TUNE_AFE_OS (2'b10),
.RX_WIDEMODE_CDR (1'b1),
.RX_XCLK_SEL ("RXDES"),
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SATA_BURST_SEQ_LEN (4'b1110),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.SHOW_REALIGN_COMMA ("TRUE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SIM_MODE ("FAST"),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL (1'b0),
.SIM_VERSION (2),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TAPDLY_SET_TX (2'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TEMPERATUR_PAR (4'b0010),
.TERM_RCAL_CFG (15'b100001000010000),
.TERM_RCAL_OVRD (3'b000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TRANS_TIME_RATE (8'h0e),
.TST_RSV0 (8'h00),
.TST_RSV1 (8'h00),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXDLY_CFG (16'h0009),
.TXDLY_LCFG (16'h0050),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXDRVBIAS_N (4'b1010),
.TXDRVBIAS_P (4'b1010),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN ("FALSE"),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPHDLY_CFG0 (16'h2020),
.TXPHDLY_CFG1 (16'h0075),
.TXPH_CFG (16'h0980),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPH_MONITOR_SEL (5'b00000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPI_CFG0 (2'b01),
.TXPI_CFG1 (2'b01),
.TXPI_CFG2 (2'b01),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPI_CFG3 (1'b0),
.TXPI_CFG4 (1'b1),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPI_CFG5 (3'b011),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_LPM (1'b0),
.TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.TXPI_PPM_CFG (8'b00000000),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPI_SYNFREQ_PPM (3'b001),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPI_VREFSEL (1'b0),
.TXPMARESET_TIME (5'b00011),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (40),
.TX_DCD_CFG (6'b000010),
.TX_DCD_EN (1'b0),
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_EML_PHI_TUNE (1'b0),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TX_INT_DATAWIDTH (1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1001111),
.TX_MARGIN_FULL_1 (7'b1001110),
.TX_MARGIN_FULL_2 (7'b1001100),
.TX_MARGIN_FULL_3 (7'b1001010),
.TX_MARGIN_FULL_4 (7'b1001000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000101),
.TX_MARGIN_LOW_2 (7'b1000011),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
.TX_MODE_SEL (3'b000),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
.TX_PROGCLK_SEL ("PREPI"),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TX_PROGDIV_CFG (0.000000),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_QPI_STATUS_EN (1'b0),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TX_RXDETECT_CFG (14'h0032),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TX_RXDETECT_REF (3'b100),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TX_SAMPLE_PERIOD (3'b111),
util_adxcvr: Delete trailing whitespaces
2016-10-05 10:51:39 +00:00
.TX_SARC_LPBK_ENB (1'b0),
.TX_XCLK_SEL ("TXOUT"),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.WB_MODE (2'b00))
i_gthe3_channel (
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CFGRESET (1'h0),
.CLKRSVD0 (1'h0),
.CLKRSVD1 (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CPLLFBCLKLOST (),
.CPLLLOCK (cpll_locked_s),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'h1),
.CPLLPD (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.CPLLREFCLKLOST (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.CPLLREFCLKSEL (3'h1),
.CPLLRESET (up_cpll_rst),
.DMONFIFORESET (1'h0),
.DMONITORCLK (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.DMONITOROUT (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.DRPADDR (up_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPDO (up_rdata_s),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.DRPEN (up_enb_int),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.DRPRDY (up_ready_s),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.DRPWE (up_wr_int),
.EVODDPHICALDONE (1'h0),
.EVODDPHICALSTART (1'h0),
.EVODDPHIDRDEN (1'h0),
.EVODDPHIDWREN (1'h0),
.EVODDPHIXRDEN (1'h0),
.EVODDPHIXWREN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.EYESCANDATAERROR (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.EYESCANMODE (1'h0),
.EYESCANRESET (1'h0),
.EYESCANTRIGGER (1'h0),
.GTGREFCLK (1'h0),
.GTHRXN (rx_n),
.GTHRXP (rx_p),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.GTHTXN (tx_n),
.GTHTXP (tx_p),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.GTNORTHREFCLK0 (1'h0),
.GTNORTHREFCLK1 (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.GTPOWERGOOD (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.GTREFCLKMONITOR (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.GTRESETSEL (1'h0),
.GTRSVD (16'h0),
.GTRXRESET (up_rx_rst),
.GTSOUTHREFCLK0 (1'h0),
.GTSOUTHREFCLK1 (1'h0),
.GTTXRESET (up_tx_rst),
.LOOPBACK (3'h0),
.LPBKRXTXSEREN (1'h0),
.LPBKTXRXSEREN (1'h0),
.PCIEEQRXEQADAPTDONE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.PCIERSTIDLE (1'h0),
.PCIERSTTXSYNCSTART (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.PCIEUSERRATEDONE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PCIEUSERRATESTART (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.PCSRSVDIN (16'h0),
.PCSRSVDIN2 (5'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.PMARSVDIN (5'h0),
.QPLL0CLK (qpll2ch_clk),
.QPLL0REFCLK (qpll2ch_ref_clk),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1CLK (qpll1_clk),
.QPLL1REFCLK (qpll1_ref_clk),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RESETEXCEPTION (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RESETOVRD (1'h0),
.RSTCLKENTX (1'h0),
.RX8B10BEN (1'h1),
.RXBUFRESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCDRFREQRESET (1'h0),
.RXCDRHOLD (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCDRLOCK (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCDROVRDEN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCDRPHDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCDRRESET (1'h0),
.RXCDRRESETRSV (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCHBONDEN (1'h0),
.RXCHBONDI (5'h0),
.RXCHBONDLEVEL (3'h0),
.RXCHBONDMASTER (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCHBONDO (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCHBONDSLAVE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXCOMMADETEN (1'h1),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCOMSASDET (),
.RXCOMWAKEDET (),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXCTRL2 (),
util_adxcvr: shared xcvr cores
2016-06-17 15:59:42 +00:00
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA ({rx_data_open_s, rx_data}),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXDFEAGCCTRL (2'h1),
.RXDFEAGCHOLD (1'h0),
.RXDFEAGCOVRDEN (1'h0),
.RXDFELFHOLD (1'h0),
.RXDFELFOVRDEN (1'h0),
.RXDFELPMRESET (1'h0),
.RXDFETAP10HOLD (1'h0),
.RXDFETAP10OVRDEN (1'h0),
.RXDFETAP11HOLD (1'h0),
.RXDFETAP11OVRDEN (1'h0),
.RXDFETAP12HOLD (1'h0),
.RXDFETAP12OVRDEN (1'h0),
.RXDFETAP13HOLD (1'h0),
.RXDFETAP13OVRDEN (1'h0),
.RXDFETAP14HOLD (1'h0),
.RXDFETAP14OVRDEN (1'h0),
.RXDFETAP15HOLD (1'h0),
.RXDFETAP15OVRDEN (1'h0),
.RXDFETAP2HOLD (1'h0),
.RXDFETAP2OVRDEN (1'h0),
.RXDFETAP3HOLD (1'h0),
.RXDFETAP3OVRDEN (1'h0),
.RXDFETAP4HOLD (1'h0),
.RXDFETAP4OVRDEN (1'h0),
.RXDFETAP5HOLD (1'h0),
.RXDFETAP5OVRDEN (1'h0),
.RXDFETAP6HOLD (1'h0),
.RXDFETAP6OVRDEN (1'h0),
.RXDFETAP7HOLD (1'h0),
.RXDFETAP7OVRDEN (1'h0),
.RXDFETAP8HOLD (1'h0),
.RXDFETAP8OVRDEN (1'h0),
.RXDFETAP9HOLD (1'h0),
.RXDFETAP9OVRDEN (1'h0),
.RXDFEUTHOLD (1'h0),
.RXDFEUTOVRDEN (1'h0),
.RXDFEVPHOLD (1'h0),
.RXDFEVPOVRDEN (1'h0),
.RXDFEVSEN (1'h0),
.RXDFEXYDEN (1'h1),
.RXDLYBYPASS (1'h1),
.RXDLYEN (1'h0),
.RXDLYOVRDEN (1'h0),
.RXDLYSRESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXDLYSRESETDONE (),
.RXELECIDLE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXELECIDLEMODE (2'h3),
.RXGEARBOXSLIP (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXHEADER (),
.RXHEADERVALID (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXLATCLK (1'h0),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMGCHOLD (1'h0),
.RXLPMGCOVRDEN (1'h0),
.RXLPMHFHOLD (1'h0),
.RXLPMHFOVRDEN (1'h0),
.RXLPMLFHOLD (1'h0),
.RXLPMLFKLOVRDEN (1'h0),
.RXLPMOSHOLD (1'h0),
.RXLPMOSOVRDEN (1'h0),
.RXMCOMMAALIGNEN (rx_calign),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXMONITOROUT (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXMONITORSEL (2'h0),
.RXOOBRESET (1'h0),
.RXOSCALRESET (1'h0),
.RXOSHOLD (1'h0),
.RXOSINTCFG (4'hd),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXOSINTDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXOSINTEN (1'h1),
.RXOSINTHOLD (1'h0),
.RXOSINTOVRDEN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXOSINTSTARTED (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXOSINTSTROBE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXOSINTTESTOVRDEN (1'h0),
.RXOSOVRDEN (1'h0),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.RXOUTCLK (rx_out_clk_s),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXOUTCLKSEL (up_rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'h0),
.RXPD (2'h0),
.RXPHALIGN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPHALIGNDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPHALIGNEN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPHALIGNERR (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPHDLYPD (1'h1),
.RXPHDLYRESET (1'h0),
.RXPHOVRDEN (1'h0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPMARESETDONE (),
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
.RXPOLARITY (RX_POLARITY),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPRBSCNTRESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPRBSERR (),
.RXPRBSLOCKED (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPRBSSEL (4'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXPRGDIVRESETDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXPROGDIVRESET (1'h0),
.RXQPIEN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXQPISENN (),
.RXQPISENP (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXRATE (rx_rate_m2),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXRATEDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXRATEMODE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXRECCLKOUT (),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.RXRESETDONE (rx_rst_done_s),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXSLIDE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXSLIDERDY (),
.RXSLIPDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXSLIPOUTCLK (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXSLIPOUTCLKRDY (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXSLIPPMA (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXSYNCALLIN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXSYNCDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXSYNCIN (1'h0),
.RXSYNCMODE (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXSYNCOUT (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.RXVALID (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.SIGVALIDCLK (1'h0),
.TSTIN (20'h0),
.TX8B10BBYPASS (8'h0),
.TX8B10BEN (1'h1),
.TXBUFDIFFCTRL (3'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXBUFSTATUS (),
.TXCOMFINISH (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXCOMINIT (1'h0),
.TXCOMSAS (1'h0),
.TXCOMWAKE (1'h0),
.TXCTRL0 (16'h0),
.TXCTRL1 (16'h0),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA ({96'd0, tx_data}),
.TXDATAEXTENDRSVD (8'h0),
.TXDEEMPH (1'h0),
.TXDETECTRX (1'h0),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXDIFFCTRL (up_tx_diffctrl),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXDIFFPD (1'h0),
.TXDLYBYPASS (1'h1),
.TXDLYEN (1'h0),
.TXDLYHOLD (1'h0),
.TXDLYOVRDEN (1'h0),
.TXDLYSRESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXDLYSRESETDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXDLYUPDOWN (1'h0),
.TXELECIDLE (1'h0),
.TXHEADER (6'h0),
.TXINHIBIT (1'h0),
.TXLATCLK (1'h0),
.TXMAINCURSOR (7'h40),
.TXMARGIN (3'h0),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.TXOUTCLK (tx_out_clk_s),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXOUTCLKSEL (up_tx_out_clk_sel),
.TXPCSRESET (1'h0),
.TXPD (2'h0),
.TXPDELECIDLEMODE (1'h0),
.TXPHALIGN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPHALIGNDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPHALIGNEN (1'h0),
.TXPHDLYPD (1'h1),
.TXPHDLYRESET (1'h0),
.TXPHDLYTSTCLK (1'h0),
.TXPHINIT (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPHINITDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPHOVRDEN (1'h0),
.TXPIPPMEN (1'h0),
.TXPIPPMOVRDEN (1'h0),
.TXPIPPMPD (1'h0),
.TXPIPPMSEL (1'h0),
.TXPIPPMSTEPSIZE (5'h0),
.TXPISOPD (1'h0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPMARESETDONE (),
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
.TXPOLARITY (TX_POLARITY),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXPOSTCURSOR (up_tx_postcursor),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPOSTCURSORINV (1'h0),
.TXPRBSFORCEERR (1'h0),
.TXPRBSSEL (4'h0),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXPRECURSOR (up_tx_precursor),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPRECURSORINV (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXPRGDIVRESETDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXPROGDIVRESET (up_tx_rst),
.TXQPIBIASEN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXQPISENN (),
.TXQPISENP (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXQPISTRONGPDOWN (1'h0),
.TXQPIWEAKPUP (1'h0),
.TXRATE (tx_rate_m2),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXRATEDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXRATEMODE (1'h0),
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-15 14:18:34 +00:00
.TXRESETDONE (tx_rst_done_s),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXSEQUENCE (7'h0),
.TXSWING (1'h0),
.TXSYNCALLIN (1'h0),
util_adxcvr- added
2016-06-14 16:18:56 +00:00
.TXSYNCDONE (),
util_adxcvr- ultrascale updates
2016-10-19 17:05:59 +00:00
.TXSYNCIN (1'h0),
.TXSYNCMODE (1'h0),
.TXSYNCOUT (),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk));
util_adxcvr- added
2016-06-14 16:18:56 +00:00
end
endgenerate
util_adxcvr- rx/tx clocks
2016-10-05 17:53:02 +00:00
generate
if (XCVR_TYPE == 2) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
generate
util_adxcvr: Fix some typo GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
2016-10-05 10:52:09 +00:00
if (XCVR_TYPE == 2) begin
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]};
assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]};
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
assign rx_pll_clk_sel_s = up_rx_sys_clk_sel;
assign tx_pll_clk_sel_s = up_tx_sys_clk_sel;
end
endgenerate
generate
util_adxcvr: Fix some typo GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
2016-10-05 10:52:09 +00:00
if (XCVR_TYPE == 2) begin
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
GTHE4_CHANNEL #(
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.ADAPT_CFG0 (16'b0001000000000000),
.ADAPT_CFG1 (16'b1100100000000000),
.ADAPT_CFG2 (16'b0000000000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.ALIGN_COMMA_WORD (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.A_RXOSCALRESET (1'b0),
.A_RXPROGDIVRESET (1'b0),
.A_RXTERMINATION (1'b1),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.A_TXDIFFCTRL (5'b10110),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.A_TXPROGDIVRESET (1'b0),
.CAPBYPASS_FORCE (1'b0),
.CBCC_DATA_SOURCE_SEL ("DECODED"),
.CDR_SWAP_MODE_EN (1'b0),
.CFOK_PWRSVE_EN (1'b1),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.CHAN_BOND_MAX_SKEW (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (16'b0010010000100100),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0101000011000000),
.CKCAL1_CFG_2 (16'b0000000000001010),
.CKCAL1_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_0 (16'b1100000011000000),
.CKCAL2_CFG_1 (16'b1000000011000000),
.CKCAL2_CFG_2 (16'b0000000000000000),
.CKCAL2_CFG_3 (16'b0000000000000000),
.CKCAL2_CFG_4 (16'b0000000000000000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.CKCAL_RSVD0 (16'b0000000010000000),
.CKCAL_RSVD1 (16'b0000010000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (12),
.CLK_COR_MIN_LAT (8),
.CLK_COR_PRECEDENCE ("TRUE"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.CLK_COR_REPEAT_WAIT (0),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0100000000),
.CLK_COR_SEQ_1_3 (10'b0100000000),
.CLK_COR_SEQ_1_4 (10'b0100000000),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_USE ("FALSE"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.CLK_COR_SEQ_LEN (1),
util_adxcvr: Expose QPLL and CPLL *_CFG attributes
2018-10-02 14:19:35 +00:00
.CPLL_CFG0 (CPLL_CFG0),
.CPLL_CFG1 (CPLL_CFG1),
.CPLL_CFG2 (CPLL_CFG2),
.CPLL_CFG3 (CPLL_CFG3),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CPLL_FBDIV (CPLL_FBDIV),
util_adxcvr_xch: GTHE4 connect CPLL_FBDIV_45 attribute
2018-09-20 15:21:14 +00:00
.CPLL_FBDIV_45 (CPLL_FBDIV_4_5),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.CPLL_INIT_CFG0 (16'b0000001010110010),
.CPLL_LOCK_CFG (16'b0000000111101000),
.CPLL_REFCLK_DIV (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CTLE3_OCAP_EXT_CTRL (3'b000),
.CTLE3_OCAP_EXT_EN (1'b0),
.DDI_CTRL (2'b00),
.DDI_REALIGN_WAIT (15),
.DEC_MCOMMA_DETECT ("TRUE"),
.DEC_PCOMMA_DETECT ("TRUE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
.DELAY_ELEC (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.DMONITOR_CFG0 (10'b0000000000),
.DMONITOR_CFG1 (8'b00000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.ES_CLK_PHASE_SEL (1'b0),
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("TRUE"),
.ES_EYE_SCAN_EN ("TRUE"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.ES_HORZ_OFFSET (12'b000000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.ES_PRESCALE (5'b00000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.ES_QUALIFIER0 (16'b0000000000000000),
.ES_QUALIFIER1 (16'b0000000000000000),
.ES_QUALIFIER2 (16'b0000000000000000),
.ES_QUALIFIER3 (16'b0000000000000000),
.ES_QUALIFIER4 (16'b0000000000000000),
.ES_QUALIFIER5 (16'b0000000000000000),
.ES_QUALIFIER6 (16'b0000000000000000),
.ES_QUALIFIER7 (16'b0000000000000000),
.ES_QUALIFIER8 (16'b0000000000000000),
.ES_QUALIFIER9 (16'b0000000000000000),
axi_adxcvr: Fix eyescan support for ultrascale plus devices
2018-10-09 09:44:09 +00:00
.ES_QUAL_MASK0 (16'b1111111111111111),
.ES_QUAL_MASK1 (16'b1111111111111111),
.ES_QUAL_MASK2 (16'b1111111111111111),
.ES_QUAL_MASK3 (16'b1111111111111111),
.ES_QUAL_MASK4 (16'b1111111111111111),
.ES_QUAL_MASK5 (16'b1111111111111111),
.ES_QUAL_MASK6 (16'b1111111111111111),
.ES_QUAL_MASK7 (16'b1111111111111111),
.ES_QUAL_MASK8 (16'b1111111111111111),
.ES_QUAL_MASK9 (16'b1111111111111111),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.ES_SDATA_MASK0 (16'b1111111111111111),
.ES_SDATA_MASK1 (16'b1111111111111111),
.ES_SDATA_MASK2 (16'b0000000011111111),
.ES_SDATA_MASK3 (16'b0000000000000000),
.ES_SDATA_MASK4 (16'b0000000000000000),
.ES_SDATA_MASK5 (16'b1111111111111111),
.ES_SDATA_MASK6 (16'b1111111111111111),
.ES_SDATA_MASK7 (16'b1111111111111111),
.ES_SDATA_MASK8 (16'b1111111111111111),
.ES_SDATA_MASK9 (16'b1111111111111111),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.EYE_SCAN_SWAP_EN (1'b0),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
.GEARBOX_MODE (5'b00000),
.ISCAN_CK_PH_SEL2 (1'b0),
.LOCAL_MASTER (1'b1),
.LPBK_BIAS_CTRL (3'b100),
.LPBK_EN_RCAL_B (1'b0),
.LPBK_EXT_RCAL (4'b1000),
.LPBK_IND_CTRL0 (3'b000),
.LPBK_IND_CTRL1 (3'b000),
.LPBK_IND_CTRL2 (3'b000),
.LPBK_RG_CTRL (4'b1110),
.OOBDIVCTL (2'b00),
.OOB_PWRUP (1'b0),
.PCI3_AUTO_REALIGN ("OVR_1K_BLK"),
.PCI3_PIPE_RX_ELECIDLE (1'b0),
.PCI3_RX_ASYNC_EBUF_BYPASS (2'b00),
.PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0),
.PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000),
.PCI3_RX_ELECIDLE_HI_COUNT (6'b000000),
.PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0),
.PCI3_RX_FIFO_DISABLE (1'b0),
.PCIE3_CLK_COR_EMPTY_THRSH (5'b00000),
.PCIE3_CLK_COR_FULL_THRSH (6'b010000),
.PCIE3_CLK_COR_MAX_LAT (5'b00100),
.PCIE3_CLK_COR_MIN_LAT (5'b00000),
.PCIE3_CLK_COR_THRSH_TIMER (6'b001000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.PCIE_BUFG_DIV_CTRL (16'b0011010100000000),
.PCIE_PLL_SEL_MODE_GEN12 (2'b10),
.PCIE_PLL_SEL_MODE_GEN3 (2'b10),
.PCIE_PLL_SEL_MODE_GEN4 (2'b10),
.PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101),
.PCIE_RXPMA_CFG (16'b0010100000001010),
.PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100),
.PCIE_TXPMA_CFG (16'b0010100000001010),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.PCS_PCIE_EN ("FALSE"),
.PCS_RSVD0 (16'b0000000000000000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (0),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.PROCESS_PAR (3'b010),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
.RCLK_SIPO_INV_EN (1'b0),
.RESET_POWERSAVE_DISABLE (1'b0),
.RTX_BUF_CML_CTRL (3'b010),
.RTX_BUF_TERM_CTRL (2'b00),
.RXBUFRESET_TIME (5'b00011),
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUF_THRESH_OVFLW (57),
.RXBUF_THRESH_OVRD ("TRUE"),
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXCDR_CFG0 (16'b0000000000000010),
.RXCDR_CFG0_GEN3 (16'b0000000000000011),
.RXCDR_CFG1 (16'b0000000000000000),
.RXCDR_CFG1_GEN3 (16'b0000000000000000),
.RXCDR_CFG2 (16'b0000001001100101),
.RXCDR_CFG2_GEN3 (16'b0000001001100101),
.RXCDR_CFG2_GEN4 (16'b0000000010110100),
.RXCDR_CFG3 (16'b0000000000010010),
.RXCDR_CFG3_GEN3 (16'b0000000000010010),
.RXCDR_CFG3_GEN4 (16'b0000000000100100),
.RXCDR_CFG4 (16'b0101110011110110),
.RXCDR_CFG4_GEN3 (16'b0101110011110110),
.RXCDR_CFG5 (16'b1011010001101011),
.RXCDR_CFG5_GEN3 (16'b0001010001101011),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXCDR_LOCK_CFG0 (16'b0010001000000001),
.RXCDR_LOCK_CFG1 (16'b1001111111111111),
.RXCDR_LOCK_CFG2 (16'b0111011111000011),
.RXCDR_LOCK_CFG3 (16'b0000000000000001),
.RXCDR_LOCK_CFG4 (16'b0000000000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXCFOK_CFG0 (16'b0000000000000000),
.RXCFOK_CFG1 (16'b1000000000010101),
.RXCFOK_CFG2 (16'b0000001010101110),
.RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000100),
.RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000100),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXDFELPMRESET_TIME (7'b0001111),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXDFELPM_KL_CFG0 (16'b0000000000000000),
.RXDFELPM_KL_CFG1 (16'b1010000011100010),
.RXDFELPM_KL_CFG2 (16'b0000000100000000),
.RXDFE_CFG0 (16'b0000101000000000),
.RXDFE_CFG1 (16'b0000000000000000),
.RXDFE_GC_CFG0 (16'b0000000000000000),
.RXDFE_GC_CFG1 (16'b1000000000000000),
.RXDFE_GC_CFG2 (16'b1111111111100000),
.RXDFE_H2_CFG0 (16'b0000000000000000),
.RXDFE_H2_CFG1 (16'b0000000000000010),
.RXDFE_H3_CFG0 (16'b0000000000000000),
.RXDFE_H3_CFG1 (16'b1000000000000010),
.RXDFE_H4_CFG0 (16'b0000000000000000),
.RXDFE_H4_CFG1 (16'b1000000000000010),
.RXDFE_H5_CFG0 (16'b0000000000000000),
.RXDFE_H5_CFG1 (16'b1000000000000010),
.RXDFE_H6_CFG0 (16'b0000000000000000),
.RXDFE_H6_CFG1 (16'b1000000000000010),
.RXDFE_H7_CFG0 (16'b0000000000000000),
.RXDFE_H7_CFG1 (16'b1000000000000010),
.RXDFE_H8_CFG0 (16'b0000000000000000),
.RXDFE_H8_CFG1 (16'b1000000000000010),
.RXDFE_H9_CFG0 (16'b0000000000000000),
.RXDFE_H9_CFG1 (16'b1000000000000010),
.RXDFE_HA_CFG0 (16'b0000000000000000),
.RXDFE_HA_CFG1 (16'b1000000000000010),
.RXDFE_HB_CFG0 (16'b0000000000000000),
.RXDFE_HB_CFG1 (16'b1000000000000010),
.RXDFE_HC_CFG0 (16'b0000000000000000),
.RXDFE_HC_CFG1 (16'b1000000000000010),
.RXDFE_HD_CFG0 (16'b0000000000000000),
.RXDFE_HD_CFG1 (16'b1000000000000010),
.RXDFE_HE_CFG0 (16'b0000000000000000),
.RXDFE_HE_CFG1 (16'b1000000000000010),
.RXDFE_HF_CFG0 (16'b0000000000000000),
.RXDFE_HF_CFG1 (16'b1000000000000010),
.RXDFE_KH_CFG0 (16'b0000000000000000),
.RXDFE_KH_CFG1 (16'b1000000000000000),
.RXDFE_KH_CFG2 (16'b0010011000010011),
.RXDFE_KH_CFG3 (16'b0100000100011100),
.RXDFE_OS_CFG0 (16'b0000000000000000),
.RXDFE_OS_CFG1 (16'b1000000000000010),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXDFE_PWR_SAVING (1'b1),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXDFE_UT_CFG0 (16'b0000000000000000),
.RXDFE_UT_CFG1 (16'b0000000000000011),
.RXDFE_UT_CFG2 (16'b0000000000000000),
.RXDFE_VP_CFG0 (16'b0000000000000000),
.RXDFE_VP_CFG1 (16'b1000000000110011),
.RXDLY_CFG (16'b0000000000010000),
.RXDLY_LCFG (16'b0000000000110000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXELECIDLE_CFG ("SIGCFG_4"),
.RXGBOX_FIFO_INIT_RD_ADDR (4),
.RXGEARBOX_EN ("FALSE"),
.RXISCANRESET_TIME (5'b00001),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXLPM_CFG (16'b0000000000000000),
.RXLPM_GC_CFG (16'b1000000000000000),
.RXLPM_KH_CFG0 (16'b0000000000000000),
.RXLPM_KH_CFG1 (16'b0000000000000010),
.RXLPM_OS_CFG0 (16'b0000000000000000),
.RXLPM_OS_CFG1 (16'b1000000000000010),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXOOB_CFG (9'b000000110),
.RXOOB_CLK_CFG ("PMA"),
.RXOSCALRESET_TIME (5'b00011),
.RXOUT_DIV (RX_OUT_DIV),
.RXPCSRESET_TIME (5'b00011),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXPHBEACON_CFG (16'b0000000000000000),
.RXPHDLY_CFG (16'b0010000001110000),
.RXPHSAMP_CFG (16'b0010000100000000),
.RXPHSLIP_CFG (16'b1001100100110011),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_AUTO_BW_SEL_BYPASS (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RXPI_CFG0 (16'b0000000000000010),
Revert "util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate" This reverts commit 9a74a40c4909d3a5f143838515a775e6d4aa5f9a.
2018-09-20 15:22:36 +00:00
.RXPI_CFG1 (16'b0000000000010101),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXPI_LPM (1'b0),
.RXPI_SEL_LC (2'b00),
.RXPI_STARTCODE (2'b00),
.RXPI_VREFSEL (1'b0),
.RXPMACLK_SEL ("DATA"),
.RXPMARESET_TIME (5'b00011),
.RXPRBS_ERR_LOOPBACK (1'b0),
.RXPRBS_LINKACQ_CNT (15),
.RXREFCLKDIV2_SEL (1'b0),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
.RX_AFE_CM_EN (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RX_BIAS_CFG0 (16'b0001010101010100),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RX_BUFFER_CFG (6'b000000),
.RX_CAPFF_SARC_ENB (1'b0),
.RX_CLK25_DIV (RX_CLK25_DIV),
.RX_CLKMUX_EN (1'b1),
.RX_CLK_SLIP_OVRD (5'b00000),
.RX_CM_BUF_CFG (4'b1010),
.RX_CM_BUF_PD (1'b0),
.RX_CM_SEL (3),
.RX_CM_TRIM (10),
.RX_CTLE3_LPF (8'b11111111),
.RX_DATA_WIDTH (40),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
.RX_DEGEN_CTRL (3'b011),
.RX_DFELPM_CFG0 (6),
.RX_DFELPM_CFG1 (1'b1),
.RX_DFELPM_KLKH_AGC_STUP_EN (1'b1),
.RX_DFE_AGC_CFG0 (2'b10),
.RX_DFE_AGC_CFG1 (4),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RX_DFE_KL_LPM_KH_CFG0 (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RX_DFE_KL_LPM_KH_CFG1 (4),
.RX_DFE_KL_LPM_KL_CFG0 (2'b01),
.RX_DFE_KL_LPM_KL_CFG1 (4),
.RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0),
.RX_DISPERR_SEQ_MATCH ("TRUE"),
.RX_DIV2_MODE_B (1'b0),
.RX_DIVRESET_TIME (5'b00001),
.RX_EN_CTLE_RCAL_B (1'b0),
.RX_EN_HI_LR (1'b1),
.RX_EXT_RL_CTRL (9'b000000000),
.RX_EYESCAN_VS_CODE (7'b0000000),
.RX_EYESCAN_VS_NEG_DIR (1'b0),
.RX_EYESCAN_VS_RANGE (2'b00),
.RX_EYESCAN_VS_UT_SIGN (1'b0),
.RX_FABINT_USRCLK_FLOP (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RX_INT_DATAWIDTH (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RX_PMA_POWER_SAVE (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.RX_PMA_RSV0 (16'b0000000000000000),
.RX_PROGDIV_CFG (0.0),
.RX_PROGDIV_RATE (16'b0000000000000001),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RX_RESLOAD_CTRL (4'b0000),
.RX_RESLOAD_OVRD (1'b0),
.RX_SAMPLE_PERIOD (3'b111),
.RX_SIG_VALID_DLY (11),
.RX_SUM_DFETAPREP_EN (1'b0),
.RX_SUM_IREF_TUNE (4'b0100),
.RX_SUM_RESLOAD_CTRL (4'b0011),
.RX_SUM_VCMTUNE (4'b0110),
.RX_SUM_VCM_OVWR (1'b0),
.RX_SUM_VREF_TUNE (3'b100),
.RX_TUNE_AFE_OS (2'b00),
.RX_VREG_CTRL (3'b101),
.RX_VREG_PDB (1'b1),
util_adxcvr: Update GHTE4 input port from the wizard
2018-10-02 15:49:18 +00:00
.RX_WIDEMODE_CDR (2'b01),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RX_WIDEMODE_CDR_GEN3 (2'b00),
.RX_WIDEMODE_CDR_GEN4 (2'b01),
.RX_XCLK_SEL ("RXDES"),
.RX_XMODE_SEL (1'b0),
.SAMPLE_CLK_PHASE (1'b0),
.SAS_12G_MODE (1'b0),
.SATA_BURST_SEQ_LEN (4'b1111),
.SATA_BURST_VAL (3'b100),
.SATA_CPLL_CFG ("VCO_3000MHZ"),
.SATA_EIDLE_VAL (3'b100),
.SHOW_REALIGN_COMMA ("TRUE"),
.SIM_MODE ("FAST"),
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("Z"),
.SRSTMODE (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TAPDLY_SET_TX (2'b00),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TEMPERATURE_PAR (4'b0010),
.TERM_RCAL_CFG (15'b100001000010001),
.TERM_RCAL_OVRD (3'b000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TRANS_TIME_RATE (8'b00001110),
.TST_RSV0 (8'b00000000),
.TST_RSV1 (8'b00000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TXDLY_CFG (16'b1000000000010000),
.TXDLY_LCFG (16'b0000000000110000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXDRVBIAS_N (4'b1010),
.TXFIFO_ADDR_CFG ("LOW"),
.TXGBOX_FIFO_INIT_RD_ADDR (4),
.TXGEARBOX_EN ("FALSE"),
.TXOUT_DIV (TX_OUT_DIV),
.TXPCSRESET_TIME (5'b00011),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TXPHDLY_CFG0 (16'b0110000001110000),
.TXPHDLY_CFG1 (16'b0000000000001111),
.TXPH_CFG (16'b0000001100100011),
.TXPH_CFG2 (16'b0000000000000000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXPH_MONITOR_SEL (5'b00000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TXPI_CFG (16'b0000000001010100),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXPI_CFG0 (2'b00),
.TXPI_CFG1 (2'b00),
.TXPI_CFG2 (2'b00),
Revert "util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate" This reverts commit 9a74a40c4909d3a5f143838515a775e6d4aa5f9a.
2018-09-20 15:22:36 +00:00
.TXPI_CFG3 (1'b0),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXPI_CFG4 (1'b0),
.TXPI_CFG5 (3'b000),
.TXPI_GRAY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_LPM (1'b0),
.TXPI_PPM (1'b0),
.TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.TXPI_PPM_CFG (8'b00000000),
.TXPI_SYNFREQ_PPM (3'b001),
.TXPI_VREFSEL (1'b0),
.TXPMARESET_TIME (5'b00011),
.TXREFCLKDIV2_SEL (1'b0),
.TXSYNC_MULTILANE (1'b1),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0),
.TX_CLK25_DIV (TX_CLK25_DIV),
.TX_CLKMUX_EN (1'b1),
.TX_DATA_WIDTH (40),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_DEEMPH2 (6'b000000),
.TX_DEEMPH3 (6'b000000),
.TX_DIVRESET_TIME (5'b00001),
.TX_DRIVE_MODE ("DIRECT"),
.TX_DRVMUX_CTRL (2),
.TX_EIDLE_ASSERT_DELAY (3'b100),
.TX_EIDLE_DEASSERT_DELAY (3'b011),
.TX_FABINT_USRCLK_FLOP (1'b0),
.TX_FIFO_BYP_EN (1'b0),
.TX_IDLE_DATA_ZERO (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TX_INT_DATAWIDTH (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_MARGIN_FULL_0 (7'b1011111),
.TX_MARGIN_FULL_1 (7'b1011110),
.TX_MARGIN_FULL_2 (7'b1011100),
.TX_MARGIN_FULL_3 (7'b1011010),
.TX_MARGIN_FULL_4 (7'b1011000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000101),
.TX_MARGIN_LOW_2 (7'b1000011),
.TX_MARGIN_LOW_3 (7'b1000010),
.TX_MARGIN_LOW_4 (7'b1000000),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TX_PHICAL_CFG0 (16'b0000000000000000),
.TX_PHICAL_CFG1 (16'b0111111000000000),
.TX_PHICAL_CFG2 (16'b0000001000000001),
.TX_PI_BIASSET (1),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TX_PI_IBIAS_MID (2'b00),
.TX_PMADATA_OPT (1'b0),
.TX_PMA_POWER_SAVE (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TX_PMA_RSV0 (16'b0000000000001000),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TX_PREDRV_CTRL (2),
.TX_PROGCLK_SEL ("PREPI"),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TX_PROGDIV_CFG (0.0),
.TX_PROGDIV_RATE (16'b0000000000000001),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TX_QPI_STATUS_EN (1'b0),
util_adxcvr: Define all GTHE4 attribute in binary This commit does not contain any functional modification. Because the wizard generates the attributes in binary, we should use binary mode too, so we can compare different configurations more easily.
2018-09-24 15:36:33 +00:00
.TX_RXDETECT_CFG (14'b00000000110010),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TX_RXDETECT_REF (4),
.TX_SAMPLE_PERIOD (3'b111),
.TX_SARC_LPBK_ENB (1'b0),
.TX_SW_MEAS (2'b00),
.TX_VREG_CTRL (3'b000),
.TX_VREG_PDB (1'b0),
.TX_VREG_VREFSEL (2'b00),
.TX_XCLK_SEL ("TXOUT"),
.USB_BOTH_BURST_IDLE (1'b0),
.USB_BURSTMAX_U3WAKE (7'b1111111),
.USB_BURSTMIN_U3WAKE (7'b1100011),
.USB_CLK_COR_EQ_EN (1'b0),
.USB_EXT_CNTL (1'b1),
.USB_IDLEMAX_POLLING (10'b1010111011),
.USB_IDLEMIN_POLLING (10'b0100101011),
.USB_LFPSPING_BURST (9'b000000101),
.USB_LFPSPOLLING_BURST (9'b000110001),
.USB_LFPSPOLLING_IDLE_MS (9'b000000100),
.USB_LFPSU1EXIT_BURST (9'b000011101),
.USB_LFPSU2LPEXIT_BURST_MS (9'b001100011),
.USB_LFPSU3WAKE_BURST_MS (9'b111110011),
.USB_LFPS_TPERIOD (4'b0011),
.USB_LFPS_TPERIOD_ACCURATE (1'b1),
.USB_MODE (1'b0),
.USB_PCIE_ERR_REP_DIS (1'b0),
.USB_PING_SATA_MAX_INIT (21),
.USB_PING_SATA_MIN_INIT (12),
.USB_POLL_SATA_MAX_BURST (8),
.USB_POLL_SATA_MIN_BURST (4),
.USB_RAW_ELEC (1'b0),
.USB_RXIDLE_P0_CTRL (1'b1),
.USB_TXIDLE_TUNE_ENABLE (1'b1),
.USB_U1_SATA_MAX_WAKE (7),
.USB_U1_SATA_MIN_WAKE (4),
.USB_U2_SAS_MAX_COM (64),
.USB_U2_SAS_MIN_COM (36),
.USE_PCS_CLK_PHASE_SEL (1'b0),
util_adxcvr: Delete trailing whitespaces
2016-10-05 10:51:39 +00:00
.Y_ALL_MODE (1'b0))
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
i_gthe4_channel (
.BUFGTCE (),
.BUFGTCEMASK (),
.BUFGTDIV (),
.BUFGTRESET (),
.BUFGTRSTMASK (),
.CDRSTEPDIR (1'd0),
.CDRSTEPSQ (1'd0),
.CDRSTEPSX (1'd0),
.CFGRESET (1'd0),
.CLKRSVD0 (1'd0),
.CLKRSVD1 (1'd0),
.CPLLFBCLKLOST (),
.CPLLFREQLOCK (1'd0),
.CPLLLOCK (cpll_locked_s),
.CPLLLOCKDETCLK (up_clk),
.CPLLLOCKEN (1'd1),
util_adxcvr: CPLLPD should be used for reset For CPLL reset the CPLLPD ports should be used, instead of the CPLLRESET. The recommended reset width is above 2us. See UG576 pg. 60 for more detail.
2018-03-05 10:40:39 +00:00
.CPLLPD (up_cpll_rst),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.CPLLREFCLKLOST (),
.CPLLREFCLKSEL (3'b001),
util_adxcvr: CPLLPD should be used for reset For CPLL reset the CPLLPD ports should be used, instead of the CPLLRESET. The recommended reset width is above 2us. See UG576 pg. 60 for more detail.
2018-03-05 10:40:39 +00:00
.CPLLRESET (1'b0),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.DMONFIFORESET (1'd0),
.DMONITORCLK (1'd0),
.DMONITOROUT (),
.DMONITOROUTCLK (),
.DRPADDR (up_addr_int[9:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPRST (1'd0),
.DRPWE (up_wr_int),
.EYESCANDATAERROR (),
axi/util_adxcvr: Add register to control eyescan reset
2018-11-08 13:54:15 +00:00
.EYESCANRESET (up_es_reset),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.EYESCANTRIGGER (1'd0),
.FREQOS (1'd0),
.GTGREFCLK (1'd0),
.GTHRXN (rx_n),
.GTHRXP (rx_p),
.GTHTXN (tx_n),
.GTHTXP (tx_p),
.GTNORTHREFCLK0 (1'd0),
.GTNORTHREFCLK1 (1'd0),
.GTPOWERGOOD (),
.GTREFCLK0 (cpll_ref_clk),
.GTREFCLK1 (1'd0),
.GTREFCLKMONITOR (),
.GTRSVD (15'd0),
.GTRXRESET (up_rx_rst),
.GTRXRESETSEL (1'd0),
.GTSOUTHREFCLK0 (1'd0),
.GTSOUTHREFCLK1 (1'd0),
.GTTXRESET (up_tx_rst),
.GTTXRESETSEL (1'd0),
.INCPCTRL (1'd0),
.LOOPBACK (3'd0),
.PCIEEQRXEQADAPTDONE (1'd0),
.PCIERATEGEN3 (),
.PCIERATEIDLE (),
.PCIERATEQPLLPD (),
.PCIERATEQPLLRESET (),
.PCIERSTIDLE (1'd0),
.PCIERSTTXSYNCSTART (1'd0),
.PCIESYNCTXSYNCDONE (),
.PCIEUSERGEN3RDY (),
.PCIEUSERPHYSTATUSRST (),
.PCIEUSERRATEDONE (1'd0),
.PCIEUSERRATESTART (),
.PCSRSVDIN (16'd0),
.PCSRSVDOUT (),
.PHYSTATUS (),
.PINRSRVDAS (),
.POWERPRESENT (),
.QPLL0CLK (qpll2ch_clk),
.QPLL0FREQLOCK (1'd0),
.QPLL0REFCLK (qpll2ch_ref_clk),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1CLK (qpll1_clk),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.QPLL1FREQLOCK (1'd0),
util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4)
2019-01-31 12:47:32 +00:00
.QPLL1REFCLK (qpll1_ref_clk),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RESETEXCEPTION (),
.RESETOVRD (1'd0),
.RX8B10BEN (1'd1),
.RXAFECFOKEN (1'b1),
.RXBUFRESET (1'd0),
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCDRFREQRESET (1'd0),
.RXCDRHOLD (1'd0),
.RXCDRLOCK (),
.RXCDROVRDEN (1'd0),
.RXCDRPHDONE (),
.RXCDRRESET (1'd0),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXCHBONDEN (1'd0),
.RXCHBONDI (5'd0),
.RXCHBONDLEVEL (3'd0),
.RXCHBONDMASTER (1'd0),
.RXCHBONDO (),
.RXCHBONDSLAVE (1'd0),
.RXCKCALDONE (),
.RXCKCALRESET (1'd0),
.RXCKCALSTART (7'd0),
.RXCLKCORCNT (),
.RXCOMINITDET (),
.RXCOMMADET (),
.RXCOMMADETEN (1'd1),
.RXCOMSASDET (),
.RXCOMWAKEDET (),
.RXCTRL0 ({rx_charisk_open_s, rx_charisk}),
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
.RXCTRL2 (),
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
.RXDATA ({rx_data_open_s, rx_data}),
.RXDATAEXTENDRSVD (),
.RXDATAVALID (),
.RXDFEAGCCTRL (2'b01),
.RXDFEAGCHOLD (1'd0),
.RXDFEAGCOVRDEN (1'd0),
.RXDFECFOKFCNUM (4'b1101),
.RXDFECFOKFEN (1'd0),
.RXDFECFOKFPULSE (1'd0),
.RXDFECFOKHOLD (1'd0),
.RXDFECFOKOVREN (1'd0),
.RXDFEKHHOLD (1'd0),
.RXDFEKHOVRDEN (1'd0),
.RXDFELFHOLD (1'd0),
.RXDFELFOVRDEN (1'd0),
.RXDFELPMRESET (1'd0),
.RXDFETAP10HOLD (1'd0),
.RXDFETAP10OVRDEN (1'd0),
.RXDFETAP11HOLD (1'd0),
.RXDFETAP11OVRDEN (1'd0),
.RXDFETAP12HOLD (1'd0),
.RXDFETAP12OVRDEN (1'd0),
.RXDFETAP13HOLD (1'd0),
.RXDFETAP13OVRDEN (1'd0),
.RXDFETAP14HOLD (1'd0),
.RXDFETAP14OVRDEN (1'd0),
.RXDFETAP15HOLD (1'd0),
.RXDFETAP15OVRDEN (1'd0),
.RXDFETAP2HOLD (1'd0),
.RXDFETAP2OVRDEN (1'd0),
.RXDFETAP3HOLD (1'd0),
.RXDFETAP3OVRDEN (1'd0),
.RXDFETAP4HOLD (1'd0),
.RXDFETAP4OVRDEN (1'd0),
.RXDFETAP5HOLD (1'd0),
.RXDFETAP5OVRDEN (1'd0),
.RXDFETAP6HOLD (1'd0),
.RXDFETAP6OVRDEN (1'd0),
.RXDFETAP7HOLD (1'd0),
.RXDFETAP7OVRDEN (1'd0),
.RXDFETAP8HOLD (1'd0),
.RXDFETAP8OVRDEN (1'd0),
.RXDFETAP9HOLD (1'd0),
.RXDFETAP9OVRDEN (1'd0),
.RXDFEUTHOLD (1'd0),
.RXDFEUTOVRDEN (1'd0),
.RXDFEVPHOLD (1'd0),
.RXDFEVPOVRDEN (1'd0),
.RXDFEXYDEN (1'd1),
.RXDLYBYPASS (1'd1),
.RXDLYEN (1'd0),
.RXDLYOVRDEN (1'd0),
.RXDLYSRESET (1'd0),
.RXDLYSRESETDONE (),
.RXELECIDLE (),
.RXELECIDLEMODE (2'b11),
.RXEQTRAINING (1'd0),
.RXGEARBOXSLIP (1'd0),
.RXHEADER (),
.RXHEADERVALID (),
.RXLATCLK (1'd0),
.RXLFPSTRESETDET (),
.RXLFPSU2LPEXITDET (),
.RXLFPSU3WAKEDET (),
.RXLPMEN (up_rx_lpm_dfe_n),
.RXLPMGCHOLD (1'd0),
.RXLPMGCOVRDEN (1'd0),
.RXLPMHFHOLD (1'd0),
.RXLPMHFOVRDEN (1'd0),
.RXLPMLFHOLD (1'd0),
.RXLPMLFKLOVRDEN (1'd0),
.RXLPMOSHOLD (1'd0),
.RXLPMOSOVRDEN (1'd0),
.RXMCOMMAALIGNEN (rx_calign),
.RXMONITOROUT (),
.RXMONITORSEL (2'd0),
.RXOOBRESET (1'd0),
.RXOSCALRESET (1'd0),
.RXOSHOLD (1'd0),
.RXOSINTDONE (),
.RXOSINTSTARTED (),
.RXOSINTSTROBEDONE (),
.RXOSINTSTROBESTARTED (),
.RXOSOVRDEN (1'd0),
.RXOUTCLK (rx_out_clk_s),
.RXOUTCLKFABRIC (),
.RXOUTCLKPCS (),
.RXOUTCLKSEL (up_rx_out_clk_sel),
.RXPCOMMAALIGNEN (rx_calign),
.RXPCSRESET (1'd0),
.RXPD (2'd0),
.RXPHALIGN (1'd0),
.RXPHALIGNDONE (),
.RXPHALIGNEN (1'd0),
.RXPHALIGNERR (),
.RXPHDLYPD (1'd1),
.RXPHDLYRESET (1'd0),
.RXPHOVRDEN (1'd0),
.RXPLLCLKSEL (rx_pll_clk_sel_s),
.RXPMARESET (1'd0),
.RXPMARESETDONE (),
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
.RXPOLARITY (RX_POLARITY),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.RXPRBSCNTRESET (1'd0),
.RXPRBSERR (),
.RXPRBSLOCKED (),
.RXPRBSSEL (4'd0),
.RXPRGDIVRESETDONE (),
.RXPROGDIVRESET (1'd0),
.RXQPIEN (1'd0),
.RXQPISENN (),
.RXQPISENP (),
.RXRATE (rx_rate_m2),
.RXRATEDONE (),
.RXRATEMODE (1'd0),
.RXRECCLKOUT (),
.RXRESETDONE (rx_rst_done_s),
.RXSLIDE (1'd0),
.RXSLIDERDY (),
.RXSLIPDONE (),
.RXSLIPOUTCLK (1'd0),
.RXSLIPOUTCLKRDY (),
.RXSLIPPMA (1'd0),
.RXSLIPPMARDY (),
.RXSTARTOFSEQ (),
.RXSTATUS (),
.RXSYNCALLIN (1'd0),
.RXSYNCDONE (),
.RXSYNCIN (1'd0),
.RXSYNCMODE (1'd0),
.RXSYNCOUT (),
.RXSYSCLKSEL (rx_sys_clk_sel_s),
.RXTERMINATION (1'd0),
.RXUSERRDY (up_rx_user_ready),
.RXUSRCLK (rx_clk),
.RXUSRCLK2 (rx_clk),
.RXVALID (),
.SIGVALIDCLK (1'd0),
.TSTIN (20'd0),
.TX8B10BBYPASS (8'd0),
.TX8B10BEN (1'd1),
.TXBUFSTATUS (),
.TXCOMFINISH (),
.TXCOMINIT (1'd0),
.TXCOMSAS (1'd0),
.TXCOMWAKE (1'd0),
.TXCTRL0 (16'd0),
.TXCTRL1 (16'd0),
.TXCTRL2 ({4'd0, tx_charisk}),
.TXDATA ({96'd0, tx_data}),
.TXDATAEXTENDRSVD (8'd0),
.TXDCCDONE (),
.TXDCCFORCESTART (1'd0),
.TXDCCRESET (1'd0),
.TXDEEMPH (2'd0),
.TXDETECTRX (1'd0),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXDIFFCTRL ({up_tx_diffctrl, 1'b0}),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXDLYBYPASS (1'd1),
.TXDLYEN (1'd0),
.TXDLYHOLD (1'd0),
.TXDLYOVRDEN (1'd0),
.TXDLYSRESET (1'd0),
.TXDLYSRESETDONE (),
.TXDLYUPDOWN (1'd0),
.TXELECIDLE (1'd0),
.TXHEADER (6'd0),
.TXINHIBIT (1'd0),
.TXLATCLK (1'd0),
.TXLFPSTRESET (1'd0),
.TXLFPSU2LPEXIT (1'd0),
.TXLFPSU3WAKE (1'd0),
.TXMAINCURSOR (7'b1000000),
.TXMARGIN (3'd0),
.TXMUXDCDEXHOLD (1'd0),
.TXMUXDCDORWREN (1'd0),
.TXONESZEROS (1'd0),
.TXOUTCLK (tx_out_clk_s),
.TXOUTCLKFABRIC (),
.TXOUTCLKPCS (),
.TXOUTCLKSEL (up_tx_out_clk_sel),
.TXPCSRESET (1'd0),
.TXPD (2'd0),
.TXPDELECIDLEMODE (1'd0),
.TXPHALIGN (1'd0),
.TXPHALIGNDONE (),
.TXPHALIGNEN (1'd0),
.TXPHDLYPD (1'd1),
.TXPHDLYRESET (1'd0),
.TXPHDLYTSTCLK (1'd0),
.TXPHINIT (1'd0),
.TXPHINITDONE (),
.TXPHOVRDEN (1'd0),
.TXPIPPMEN (1'd0),
.TXPIPPMOVRDEN (1'd0),
.TXPIPPMPD (1'd0),
.TXPIPPMSEL (1'd0),
.TXPIPPMSTEPSIZE (5'd0),
.TXPISOPD (1'd0),
.TXPLLCLKSEL (tx_pll_clk_sel_s),
.TXPMARESET (1'd0),
.TXPMARESETDONE (),
xilinx: util_adxcvr: Add support for lane polarity inversion Some designs choose to swap the positive and negative side of the of the JESD204 lanes. One reason for this would be because it can simplify the PCB layout. The polarity is in most cases also only applied to a subset of the used lanes. Add support for this to the util_adxcvr module. This done by adding new parameter to the modules that allows to specify a per lane polarity inversion. Each bit in the parameter corresponds to one lane. If the bit is set the polarity is inverted for his lane. E.g. setting the parameter to 0xc will invert the 3rd and 4th lane. The setting is forwarded to the Xilinx transceiver for the corresponding lane. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-04 14:27:49 +00:00
.TXPOLARITY (TX_POLARITY),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXPOSTCURSOR (up_tx_postcursor),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXPRBSFORCEERR (1'd0),
.TXPRBSSEL (4'd0),
axi|util_adxcvr: Expose TX configurable driver ports Expose the TX configurable driver ports, more specifically the TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This provides a soft tunning capability of the transmit side of the transceivers, in cases where the insertion loss of the channel is too high or low, comparing to the default value supported by the default configuration of the GTs. You can find information about these configuration ports under the section called 'TX Configurable Driver' in the GT transceivers user guide. (UG476, UG576)
2018-10-01 15:36:39 +00:00
.TXPRECURSOR (up_tx_precursor),
util_adxcvr- ultrascale+ initial commit
2016-10-03 19:13:03 +00:00
.TXPRGDIVRESETDONE (),
.TXPROGDIVRESET (up_tx_rst),
.TXQPIBIASEN (1'd0),
.TXQPISENN (),
.TXQPISENP (),
.TXQPIWEAKPUP (1'd0),
.TXRATE (tx_rate_m2),
.TXRATEDONE (),
.TXRATEMODE (1'd0),
.TXRESETDONE (tx_rst_done_s),
.TXSEQUENCE (7'd0),
.TXSWING (1'd0),
.TXSYNCALLIN (1'd0),
.TXSYNCDONE (),
.TXSYNCIN (1'd0),
.TXSYNCMODE (1'd0),
.TXSYNCOUT (),
.TXSYSCLKSEL (tx_sys_clk_sel_s),
.TXUSERRDY (up_tx_user_ready),
.TXUSRCLK (tx_clk),
.TXUSRCLK2 (tx_clk));
end
endgenerate
util_adxcvr: Delete trailing whitespaces
2016-10-05 10:51:39 +00:00
endmodule
util_adxcvr- added
2016-06-14 16:18:56 +00:00
// ***************************************************************************
// ***************************************************************************