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pluto_hdl_adi/library/axi_ad6676/axi_ad6676_ip.tcl

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Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad6676
adi_ip_files axi_ad6676 [list \
"axi_ad6676.v" ]
adi_ip_properties axi_ad6676
axi_ad6676: Use the generic JESD204 ADC receiver core Replace the axi_ad6676 implementation with the new generic JESD204 interface ADC core. The replacement is functionally equivalent, except that the converter clock ratio is now correctly reported as 2 rather than 1 as before. Also the adc_rst output port is removed. It is not used in any design. The current guidelines for the reset for the JESD204 subsystem is to use an external reset generator. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-05 17:31:10 +00:00
adi_ip_add_core_dependencies { \
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
}
axi_ad6676: Update the core, sof interface added
2016-11-09 14:42:42 +00:00
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
axi_*: Infer clock and reset signals of an IP A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip
2018-02-15 08:41:14 +00:00
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
Add .gitattributes file Add .gitattributes file which sets up the eol encoding handling. This will make sure that we get a uniform eol encoding across different operating systems. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 09:04:19 +00:00
ipx::save_core [ipx::current_core]