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pluto_hdl_adi/library/jesd204/scripts/jesd204.tcl

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Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
#
# The ADI JESD204 Core is released under the following license, which is
# different than all other HDL cores in this repository.
#
# Please read this, and understand the freedoms and responsibilities you have
# by using this source code/core.
#
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
#
# This core is free software, you can use run, copy, study, change, ask
# questions about and improve this core. Distribution of source, or resulting
# binaries (including those inside an FPGA or ASIC) require you to release the
# source of the entire project (excluding the system libraries provide by the
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License version 2
# along with this source code, and binary. If not, see
# <http://www.gnu.org/licenses/>.
#
# Commercial licenses (with commercial support) of this JESD204 core are also
# available under terms different than the General Public License. (e.g. they
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
# core with any corresponding source code.) For these alternate terms you must
# purchase a license from Analog Devices Technology Licensing Office. Users
# interested in such a license should contact jesd204-licensing@analog.com for
# more information. This commercial license is sub-licensable (if you purchase
# chips from Analog Devices, incorporate them into your PCB level product, and
# purchase a JESD204 license, end users of your product will also have a
# license to use this core in a commercial setting without releasing their
# source code).
#
# In addition, we kindly ask you to acknowledge ADI in any program, application
# or publication in which you use this JESD204 HDL core. (You are not required
# to do so; it is up to your common sense to decide whether you want to comply
# with this request or not.) For general publications, we suggest referencing :
# “The design and implementation of the JESD204 HDL Core used in this project
# is copyright © 2016-2017, Analog Devices, Inc.”
#
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
proc adi_axi_jesd204_tx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
jesd204: support for 16 lanes
2019-10-31 11:16:25 +00:00
if {$num_lanes < 1 || $num_lanes > 16} {
return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
}
jesd204_tx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a TX link this means that the FPGA receives multiple SYNC signals, one for each link. The state machine of the TX link peripheral must combine those SYNC signals into a single SYNC signal that is asserted when either of the external SYNC signals is asserted. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the use case profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the TX FSM.
2018-03-29 09:38:34 +00:00
if {$num_links < 1 || $num_links > 8} {
return -code 1 "ERROR: Invalid number of JESD204B links. (Supported range 1-8)"
}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
startgroup
set result [catch {
create_bd_cell -type hier $ip_name
ad_ip_instance axi_jesd204_tx "${ip_name}/tx_axi"
ad_ip_instance jesd204_tx "${ip_name}/tx"
ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LANES $num_lanes
jesd204_tx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a TX link this means that the FPGA receives multiple SYNC signals, one for each link. The state machine of the TX link peripheral must combine those SYNC signals into a single SYNC signal that is asserted when either of the external SYNC signals is asserted. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the use case profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the TX FSM.
2018-03-29 09:38:34 +00:00
ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LINKS $num_links
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
ad_ip_parameter "${ip_name}/tx_axi" CONFIG.LINK_MODE $link_mode
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LANES $num_lanes
jesd204_tx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a TX link this means that the FPGA receives multiple SYNC signals, one for each link. The state machine of the TX link peripheral must combine those SYNC signals into a single SYNC signal that is asserted when either of the external SYNC signals is asserted. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the use case profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the TX FSM.
2018-03-29 09:38:34 +00:00
ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LINKS $num_links
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
ad_ip_parameter "${ip_name}/tx" CONFIG.LINK_MODE $link_mode
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/tx_axi/core_reset" "${ip_name}/tx/reset"
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
ad_connect "${ip_name}/tx_axi/device_reset" "${ip_name}/tx/device_reset"
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
if {$link_mode == 1} {ad_connect "${ip_name}/tx_axi/tx_ctrl" "${ip_name}/tx/tx_ctrl"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/tx_axi/tx_cfg" "${ip_name}/tx/tx_cfg"
ad_connect "${ip_name}/tx/tx_event" "${ip_name}/tx_axi/tx_event"
ad_connect "${ip_name}/tx/tx_status" "${ip_name}/tx_axi/tx_status"
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
if {$link_mode == 1} {ad_connect "${ip_name}/tx/tx_ilas_config" "${ip_name}/tx_axi/tx_ilas_config"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
# Control interface
create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
create_bd_pin -dir O -type intr "${ip_name}/irq"
ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tx_axi/s_axi_aclk"
ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tx_axi/s_axi_aresetn"
ad_connect "${ip_name}/s_axi" "${ip_name}/tx_axi/s_axi"
ad_connect "${ip_name}/tx_axi/irq" "${ip_name}/irq"
# JESD204 processing
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
create_bd_pin -dir I -type clk "${ip_name}/link_clk"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
create_bd_pin -dir I -type clk "${ip_name}/device_clk"
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
if {$link_mode == 1} {create_bd_pin -dir I -from [expr $num_links - 1] -to 0 "${ip_name}/sync"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
create_bd_pin -dir I "${ip_name}/sysref"
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/tx_data"
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
ad_connect "${ip_name}/link_clk" "${ip_name}/tx_axi/core_clk"
ad_connect "${ip_name}/link_clk" "${ip_name}/tx/clk"
ad_connect "${ip_name}/device_clk" "${ip_name}/tx_axi/device_clk"
ad_connect "${ip_name}/device_clk" "${ip_name}/tx/device_clk"
jesd204/scripts: Add 64b mode to Tx scripting
2019-10-03 08:32:49 +00:00
if {$link_mode == 1} {ad_connect "${ip_name}/sync" "${ip_name}/tx/sync"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/sysref" "${ip_name}/tx/sysref"
ad_connect "${ip_name}/tx_data" "${ip_name}/tx/tx_data"
for {set i 0} {$i < $num_lanes} {incr i} {
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 "${ip_name}/tx_phy${i}"
ad_connect "${ip_name}/tx/tx_phy${i}" "${ip_name}/tx_phy${i}"
}
} resulttext resultoptions]
dict unset resultoptions -level
endgroup
if {$result != 0} {
undo -quiet
}
return -options $resultoptions $resulttext
}
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
proc adi_axi_jesd204_rx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
jesd204: support for 16 lanes
2019-10-31 11:16:25 +00:00
if {$num_lanes < 1 || $num_lanes > 16} {
return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
}
jesd204_rx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a RX link this means that the SYNC signal needs to be propagated from the FPGA to each converter. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the usecase profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the RX FSM.
2018-03-27 14:45:46 +00:00
if {$num_links < 1 || $num_links > 8} {
return -code 1 "ERROR: Invalid number of JESD204B links. (Supported range 1-8)"
}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
startgroup
set result [catch {
create_bd_cell -type hier $ip_name
ad_ip_instance axi_jesd204_rx "${ip_name}/rx_axi"
ad_ip_instance jesd204_rx "${ip_name}/rx"
ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LANES $num_lanes
jesd204_rx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a RX link this means that the SYNC signal needs to be propagated from the FPGA to each converter. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the usecase profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the RX FSM.
2018-03-27 14:45:46 +00:00
ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LINKS $num_links
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
ad_ip_parameter "${ip_name}/rx_axi" CONFIG.LINK_MODE $link_mode
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LANES $num_lanes
jesd204_rx: Add dynamic multi-link support A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For a RX link this means that the SYNC signal needs to be propagated from the FPGA to each converter. Dynamic multi-link support must allow to select to which converter devices on the multi-link the SYNC signal is propagated too. This is useful when depending on the usecase profile some converter devices are supposed to be disabled. Add the cfg_links_disable[0x081] register for multi-link control and propagate its value to the RX FSM.
2018-03-27 14:45:46 +00:00
ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LINKS $num_links
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
ad_ip_parameter "${ip_name}/rx" CONFIG.LINK_MODE $link_mode
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/rx_axi/core_reset" "${ip_name}/rx/reset"
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
ad_connect "${ip_name}/rx_axi/device_reset" "${ip_name}/rx/device_reset"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/rx_axi/rx_cfg" "${ip_name}/rx/rx_cfg"
ad_connect "${ip_name}/rx/rx_event" "${ip_name}/rx_axi/rx_event"
ad_connect "${ip_name}/rx/rx_status" "${ip_name}/rx_axi/rx_status"
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
if {$link_mode == 1} {ad_connect "${ip_name}/rx/rx_ilas_config" "${ip_name}/rx_axi/rx_ilas_config"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
# Control interface
create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
create_bd_pin -dir O -type intr "${ip_name}/irq"
ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/rx_axi/s_axi_aclk"
ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/rx_axi/s_axi_aresetn"
ad_connect "${ip_name}/s_axi" "${ip_name}/rx_axi/s_axi"
ad_connect "${ip_name}/rx_axi/irq" "${ip_name}/irq"
# JESD204 processing
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
create_bd_pin -dir I -type clk "${ip_name}/link_clk"
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
create_bd_pin -dir I -type clk "${ip_name}/device_clk"
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
if {$link_mode == 1} {create_bd_pin -dir O -from [expr $num_links - 1] -to 0 "${ip_name}/sync"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
create_bd_pin -dir I "${ip_name}/sysref"
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
if {$link_mode == 1} {create_bd_pin -dir O "${ip_name}/phy_en_char_align"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
# create_bd_pin -dir I "${ip_name}/phy_ready"
create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_eof"
create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_sof"
# create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/rx_data"
create_bd_pin -dir O "${ip_name}/rx_data_tvalid"
create_bd_pin -dir O -from [expr $num_lanes * 32 - 1] -to 0 "${ip_name}/rx_data_tdata"
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
ad_connect "${ip_name}/link_clk" "${ip_name}/rx_axi/core_clk"
ad_connect "${ip_name}/link_clk" "${ip_name}/rx/clk"
ad_connect "${ip_name}/device_clk" "${ip_name}/rx_axi/device_clk"
ad_connect "${ip_name}/device_clk" "${ip_name}/rx/device_clk"
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
if {$link_mode == 1} {ad_connect "${ip_name}/rx/sync" "${ip_name}/sync"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/sysref" "${ip_name}/rx/sysref"
# ad_connect "${ip_name}/phy_ready" "${ip_name}/rx/phy_ready"
scripts/jesd204.tcl: Added 64b mode to Rx scripting
2019-10-10 07:34:23 +00:00
if {$link_mode == 1} {ad_connect "${ip_name}/rx/phy_en_char_align" "${ip_name}/phy_en_char_align"}
Add ADI JESD204 link layer cores The ADI JESD204 link layer cores are a implementation of the JESD204 link layer. They are responsible for handling the control signals (like SYNC and SYSREF) and controlling the link state machine as well as performing per-lane (de-)scrambling and character replacement. Architecturally the cores are separated into two components. 1) Protocol processing cores (jesd204_rx, jesd204_tx). These cores take care of the JESD204 protocol handling. They have configuration and status ports that allows to configure their behaviour and monitor the current state. The processing cores run entirely in the lane_rate/40 clock domain. They have a upstream and a downstream port that accept and generate raw PHY level data and transport level payload data (which is which depends on the direction of the core). 2) Configuration interface cores (axi_jesd204_rx, axi_jesd204_tx). The configuration interface cores provide a register map interface that allow access to the to the configuration and status interfaces of the processing cores. The configuration cores are responsible for implementing the clock domain crossing between the lane_rate/40 and register map clock domain. These new cores are compatible to all ADI converter products using the JESD204 interface. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-17 17:28:50 +00:00
ad_connect "${ip_name}/rx/rx_data" "${ip_name}/rx_data_tdata"
ad_connect "${ip_name}/rx/rx_valid" "${ip_name}/rx_data_tvalid"
ad_connect "${ip_name}/rx/rx_eof" "${ip_name}/rx_eof"
ad_connect "${ip_name}/rx/rx_sof" "${ip_name}/rx_sof"
for {set i 0} {$i < $num_lanes} {incr i} {
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 "${ip_name}/rx_phy${i}"
ad_connect "${ip_name}/rx/rx_phy${i}" "${ip_name}/rx_phy${i}"
}
} resulttext resultoptions]
dict unset resultoptions -level
endgroup
if {$result != 0} {
undo -quiet
}
return -options $resultoptions $resulttext
}
jesd204: create wrappers around TPLs in BD
2018-11-01 10:38:13 +00:00
# L M S N & NP
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width {link_layer_bytes_per_beat 4} {dma_sample_width 16}} {
jesd204: create wrappers around TPLs in BD
2018-11-01 10:38:13 +00:00
scripts/jesd204.tcl: add support for more lanes and converters for TPLs
2019-11-15 13:15:19 +00:00
if {$num_of_lanes < 1 || $num_of_lanes > 16} {
return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
jesd204: create wrappers around TPLs in BD
2018-11-01 10:38:13 +00:00
}
# F = (M * N * S) / (L * 8)
set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)];
# one beat per lane must accommodate at least one frame
set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)]
# datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N)
set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)];
startgroup
set result [catch {
create_bd_cell -type hier $ip_name
# Control interface
create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
# Interface to link layer
create_bd_pin -dir I -type clk "${ip_name}/link_clk"
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link"
# Interface to application layer
create_bd_pin -dir I "${ip_name}/dac_dunf"
for {set i 0} {$i < $num_of_converters} {incr i} {
create_bd_pin -dir O "${ip_name}/dac_enable_${i}"
create_bd_pin -dir O "${ip_name}/dac_valid_${i}"
create_bd_pin -dir I "${ip_name}/dac_data_${i}"
}
# Generic TPL core
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
2020-04-16 14:32:03 +00:00
ad_ip_instance ad_ip_jesd204_tpl_dac "${ip_name}/dac_tpl_core" [list \
jesd204: create wrappers around TPLs in BD
2018-11-01 10:38:13 +00:00
NUM_LANES $num_of_lanes \
NUM_CHANNELS $num_of_converters \
SAMPLES_PER_FRAME $samples_per_frame \
CONVERTER_RESOLUTION $sample_width \
BITS_PER_SAMPLE $sample_width \
OCTETS_PER_BEAT $tpl_bytes_per_beat \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
2020-10-27 15:40:37 +00:00
DMA_BITS_PER_SAMPLE $dma_sample_width
jesd204: create wrappers around TPLs in BD
2018-11-01 10:38:13 +00:00
]
jesd204/scripts: TPL add support for M=1 When only one converter is used there is no need for concatenation and slicer cores. In that case the TPL will connect to port 0 from the application layer.
2019-01-22 08:35:51 +00:00
if {$num_of_converters > 1} {
jesd204/scripts: fix indentation
2019-01-22 08:37:41 +00:00
# Concatenation and slicer cores
jesd204: DAC TPL to support 64 channels
2020-02-15 02:41:26 +00:00
# xconcat limited to 32 input ports
for {set i 0} {$i < $num_of_converters} {incr i 32} {
ad_ip_instance xlconcat "${ip_name}/data_concat[expr $i/32]" [list \
NUM_PORTS [expr min(32,$num_of_converters-$i)] \
]
}
# main concat
if {$num_of_converters > 32} {
ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
NUM_PORTS [expr int(ceil(double($num_of_converters)/32))] \
]
}
jesd204/scripts: fix indentation
2019-01-22 08:37:41 +00:00
for {set i 0} {$i < $num_of_converters} {incr i} {
ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
]
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
]
}
jesd204/scripts: TPL add support for M=1 When only one converter is used there is no need for concatenation and slicer cores. In that case the TPL will connect to port 0 from the application layer.
2019-01-22 08:35:51 +00:00
}
jesd204: create wrappers around TPLs in BD
2018-11-01 10:38:13 +00:00
# Create connections
# TPL configuration interface
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/dac_tpl_core/s_axi_aclk"
ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/dac_tpl_core/s_axi_aresetn"
ad_connect "${ip_name}/s_axi" "${ip_name}/dac_tpl_core/s_axi"
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# TPL - link layer
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/dac_tpl_core/link_clk ${ip_name}/link_clk
ad_connect ${ip_name}/dac_tpl_core/link ${ip_name}/link
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# TPL - app layer
jesd204/scripts: TPL add support for M=1 When only one converter is used there is no need for concatenation and slicer cores. In that case the TPL will connect to port 0 from the application layer.
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if {$num_of_converters > 1} {
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for {set i 0} {$i < $num_of_converters} {incr i} {
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/dac_tpl_core/enable ${ip_name}/enable_slice_$i/Din
ad_connect ${ip_name}/dac_tpl_core/dac_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/dac_enable_$i
ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/dac_valid_$i
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ad_connect ${ip_name}/dac_data_$i ${ip_name}/data_concat[expr $i/32]/In[expr $i%32]
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}
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if {$num_of_converters > 32} {
# wire all concatenators together
for {set i 0} {$i < $num_of_converters} {incr i 32} {
ad_connect ${ip_name}/data_concat[expr $i/32]/dout ${ip_name}/data_concat/In[expr $i/32]
}
ad_connect ${ip_name}/data_concat/dout ${ip_name}/dac_tpl_core/dac_ddata
} else {
ad_connect ${ip_name}/data_concat0/dout ${ip_name}/dac_tpl_core/dac_ddata
}
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} else {
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/dac_data_0 ${ip_name}/dac_tpl_core/dac_ddata
ad_connect ${ip_name}/dac_tpl_core/enable ${ip_name}/dac_enable_0
ad_connect ${ip_name}/dac_tpl_core/dac_valid ${ip_name}/dac_valid_0
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}
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/dac_dunf ${ip_name}/dac_tpl_core/dac_dunf
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} resulttext resultoptions]
dict unset resultoptions -level
endgroup
if {$result != 0} {
undo -quiet
}
return -options $resultoptions $resulttext
}
# L M S N & NP
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
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proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width {link_layer_bytes_per_beat 4} {dma_sample_width 16}} {
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if {$num_of_lanes < 1 || $num_of_lanes > 16} {
return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-16)"
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}
# F = (M * N * S) / (L * 8)
set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)];
# one beat per lane must accommodate at least one frame
set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)]
# datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N)
set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)];
startgroup
set result [catch {
create_bd_cell -type hier $ip_name
# Control interface
create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk"
create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn"
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi"
# Interface to link layer
create_bd_pin -dir I -type clk "${ip_name}/link_clk"
#create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link"
create_bd_pin -dir I "${ip_name}/link_sof"
create_bd_pin -dir I "${ip_name}/link_valid"
create_bd_pin -dir I "${ip_name}/link_data"
# Interface to application layer
create_bd_pin -dir I "${ip_name}/adc_dovf"
for {set i 0} {$i < $num_of_converters} {incr i} {
create_bd_pin -dir O "${ip_name}/adc_enable_${i}"
create_bd_pin -dir O "${ip_name}/adc_valid_${i}"
create_bd_pin -dir O "${ip_name}/adc_data_${i}"
}
# Generic TPL core
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_ip_instance ad_ip_jesd204_tpl_adc "${ip_name}/adc_tpl_core" [list \
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NUM_LANES $num_of_lanes \
NUM_CHANNELS $num_of_converters \
SAMPLES_PER_FRAME $samples_per_frame \
CONVERTER_RESOLUTION $sample_width \
BITS_PER_SAMPLE $sample_width \
OCTETS_PER_BEAT $tpl_bytes_per_beat \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
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DMA_BITS_PER_SAMPLE $dma_sample_width
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]
jesd204/scripts: TPL add support for M=1 When only one converter is used there is no need for concatenation and slicer cores. In that case the TPL will connect to port 0 from the application layer.
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if {$num_of_converters > 1} {
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# Slicer cores
for {set i 0} {$i < $num_of_converters} {incr i} {
ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
jesd204: Xilinx: NP=12 support To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.
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DIN_WIDTH [expr $dma_sample_width*$samples_per_channel*$num_of_converters] \
DIN_FROM [expr $dma_sample_width*$samples_per_channel*($i+1)-1] \
DIN_TO [expr $dma_sample_width*$samples_per_channel*$i] \
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]
ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
]
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
]
}
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}
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# Create connections
# TPL configuration interface
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
2020-04-16 14:32:03 +00:00
ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/adc_tpl_core/s_axi_aclk"
ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/adc_tpl_core/s_axi_aresetn"
ad_connect "${ip_name}/s_axi" "${ip_name}/adc_tpl_core/s_axi"
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# TPL - link layer
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/adc_tpl_core/link_clk ${ip_name}/link_clk
#ad_connect ${ip_name}/adc_tpl_core/link ${ip_name}/link
ad_connect ${ip_name}/adc_tpl_core/link_sof ${ip_name}/link_sof
ad_connect ${ip_name}/adc_tpl_core/link_data ${ip_name}/link_data
ad_connect ${ip_name}/adc_tpl_core/link_valid ${ip_name}/link_valid
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# TPL - app layer
jesd204/scripts: TPL add support for M=1 When only one converter is used there is no need for concatenation and slicer cores. In that case the TPL will connect to port 0 from the application layer.
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if {$num_of_converters > 1} {
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for {set i 0} {$i < $num_of_converters} {incr i} {
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/adc_tpl_core/adc_data ${ip_name}/data_slice_$i/Din
ad_connect ${ip_name}/adc_tpl_core/enable ${ip_name}/enable_slice_$i/Din
ad_connect ${ip_name}/adc_tpl_core/adc_valid ${ip_name}/valid_slice_$i/Din
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ad_connect ${ip_name}/data_slice_$i/Dout ${ip_name}/adc_data_$i
ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/adc_enable_$i
ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/adc_valid_$i
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}
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} else {
scripts/jesd204.tcl: rename tpl core instance Having the same name for dac and adc TPLs creates conflict in the address segment naming having random names associated to the segments. This causes difficulties during scripting of the project in test bench mode.
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ad_connect ${ip_name}/adc_tpl_core/adc_data ${ip_name}/adc_data_0
ad_connect ${ip_name}/adc_tpl_core/enable ${ip_name}/adc_enable_0
ad_connect ${ip_name}/adc_tpl_core/adc_valid ${ip_name}/adc_valid_0
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}
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ad_connect ${ip_name}/adc_dovf ${ip_name}/adc_tpl_core/adc_dovf
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} resulttext resultoptions]
dict unset resultoptions -level
endgroup
if {$result != 0} {
undo -quiet
}
return -options $resultoptions $resulttext
}
jesd204/scripts: Helper procedure for TPL width calculation
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# Calculate Link Layer interface width towards Transport Layer
# TPL width must be set to an integer multiple of F
proc adi_jesd204_calc_tpl_width {link_datapath_width jesd_l jesd_m jesd_s jesd_np} {
set jesd_f [expr ($jesd_m*$jesd_s*$jesd_np)/(8*$jesd_l)]
# For F=3,6,12 get first pow 2 multiple of F greater than link_datapath_width
if {$jesd_f % 3 == 0} {
set np12_datapath_width $jesd_f
while {$np12_datapath_width < $link_datapath_width} {
set np12_datapath_width [expr 2*$np12_datapath_width]
}
return $np12_datapath_width
} else {
return [expr max($jesd_f,$link_datapath_width)]
}
}